Secure bypass of low-level configuration in reconfiguration of a computing system

Patent metadata

Field	Value
Publication number	US-9959124-B1
Application number	US-201414498428-A
Country	US
Kind code	B1
Filing date	Sep 26, 2014
Priority date	Sep 26, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

In an embodiment, a system includes a functional unit that remains powered when the remainder of the system is powered off. The functional unit may, in response to a transition from a first power state to a second power state, retrieve configuration information from a read-only memory. In some embodiments, may be configured to store at least a portion of the configured information in a secure portion of a memory included in the functional unit and then lock the secure portion of the memory. The functional unit may then complete the transition to the second power state.

First claim

What is claimed is:

1. An apparatus, comprising:
a peripheral processing circuit;
one or more sensors;
a memory included in an always-on power domain;
a plurality of registers included in the always-on power domain; and
a processor included in the always-on power domain, wherein the processor is, in response to a change in a programmable configuration of the peripheral processing circuit, configured to:
determine capabilities of the peripheral processing circuit;
determine one or more configuration parameters for the peripheral processing circuit using the determined capabilities;
store the one or more configuration parameters in the peripheral processing circuit; and
during a reduced power mode of the peripheral processing circuit, the processor is further configured to:
read data from at least one of the one or more sensors;
filter the data read from the at least one of the one or more sensors; and
initiate a power mode change of the peripheral processing circuit based on a comparison of an amount of available storage space in the memory to a threshold value;

following a power mode change of the peripheral processing circuit, the processor is further configured to:
store at least a portion of the configuration parameters in a portion of the memory;
store information indicative of a location of the portion of the memory in at least one register of the plurality of registers; and
lock the portion of the memory and the at least one register from further updates.

2. The apparatus of claim 1 , wherein to lock the portion of the memory and the at least one register, the processor is further configured to write a predetermined value into a given register of the plurality of registers.

3. The apparatus of claim 2 , further comprising a circuit configured to prevent writes to the portion of the memory and the at least one register, and wherein the processor is further configured to activate the circuit in response to a determination that the predetermined value has been stored into the given register of the plurality of registers.

4. The apparatus of claim 2 , wherein the processor is further configured to set a size of the portion of the memory using the information indicative of the location of the portion of the memory.

5. The apparatus of claim 1 , wherein peripheral processing circuit includes a graphics processing circuit.

6. A method for operating a computing system, the method comprising:
initiating a transition from a first power state to a second power state, wherein a power consumed by the computing system in the second power state is greater than a power consumed by the computing system in the first power state;
retrieving configuration information from a memory;
in response to determining a peripheral processing circuit is in a reduced power mode:
reading data, by a processor included in an always-on power domain, from at least one of one or more sensors;
filtering, by the processor, the data read from the at least one of the one or more sensors; and
initiate a power mode change of the peripheral processing circuit based on a comparison of an amount of available storage space in the memory to a threshold value;

in response to a change in a programmable configuration of the peripheral processing circuit:
determining, by the processor included in an always-on power domain, capabilities of the peripheral processing circuit;
determining one or more configuration parameters for the peripheral processing circuit using the determined capabilities;
storing the one or more configuration parameters in the peripheral processing circuit; and
following a power mode change of the peripheral processing circuit:
storing at least a portion of the configuration parameters in a portion of a memory included in the always-on power domain;
storing information indicative of a location of the portion of the memory in at least one register of a plurality of registers included in the always-on power domain; and
locking the portion of the memory and the at least one register from further updates.

7. The method of claim 6 , wherein locking the portion of the memory and the at least one register comprises writing a predetermined value into a given register of the plurality of registers.

8. The method of claim 7 , wherein locking the portion of the memory further comprises preventing writes to the portion of the memory in response to the writing of the predetermined value into the given register of the plurality of registers.

9. The method of claim 7 , further comprising setting a size of the portion of the memory using information indicative of the location of the portion of the memory.

10. The method of claim 6 , further comprising reading at least the portion of the configuration parameters from the memory in response to the power mode change of the peripheral processing circuit.

11. The method of claim 6 , further comprising unlocking the portion of the memory and the at least one register in response to entry into a power off state.

12. A system, comprising:
a first processor;
a first memory;
one or more sensors;
a second memory included in an always-on power domain;
a plurality of registers included in the always-on power domain; and
a second processor included in an always-on power domain, wherein the second processor is configured to:
while the first processor is in a reduced power mode:
read data from at least one of the one or more sensors;
filter the data read from the at least one of the one or more sensors; and
initiate a power mode change of the peripheral processing circuit based on a comparison of an amount of available storage space in the memory to a threshold value;

in response to a change in a programmable configuration of the first processor:
determine capabilities of the first processor;
determine one or more configuration parameters for the first processor using the determined capabilities;
store the one or more configuration parameters in the first processor;
store the one or more configuration parameters in a portion of the second memory;

following a power mode change of the first processor:
store at least a portion of the configuration parameters in a portion of the second memory;
store information indicative of a location of the portion of the second memory in at least one register of the plurality of registers; and
lock the portion of the second memory and the at least one register of the plurality of registers from further updates.

13. The system of claim 12 , wherein to lock the portion of the second memory and the at least one register the second processor is further configured to write a predetermined value into a given register of the plurality of registers.

14. The system of claim 13 , wherein the second processor is further configured to prevent writes to the portion of the second memory and the at least one register in response to a determination that a predetermined value was stored into the given register of the plurality of registers.

15. The system of claim 13 , wherein the second processor is further configured to set a size of the portion of the second memory using the information indicative of the location of the portion of the second memory.

16. The system of claim 12 , wherein the first processor is configured to process graphics data.

Assignees

• Apple Inc

Inventors

• Herbeck Gilbert H
• Gulati Manu
• Machnicki Erik P
• Paaske Timothy R

Classifications

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title