Systems and methods to separate power domains in a processing device

Patent metadata

Field	Value
Publication number	US-9958918-B2
Application number	US-201615162452-A
Country	US
Kind code	B2
Filing date	May 23, 2016
Priority date	May 23, 2016
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a processing core having a plurality of sub cores;
a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core; and
a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device, wherein each power rail includes a conductive line for ground (VSS) and a conductive line for power source (VDD), wherein the conductive line for VDD includes the discontinuity.

2. The semiconductor device of claim 1 , wherein each of the cells comprises:
a first VDD contact; and
a second VDD contact, the first and second VDD contacts being built within a common N-type doped region of a substrate of the semiconductor device.

3. The semiconductor device of claim 2 , wherein the first VDD contact is coupled to the respective power rail on a side of the boundary corresponding to the first sub core, and wherein the second VDD contact is coupled to the respective power rail on a side of the boundary corresponding to the second sub core.

4. The semiconductor device of claim 2 , wherein the first VDD contact and the second VDD contact are not directly coupled with doped semiconductor material of the N-type doped region.

5. A semiconductor device comprising:
a processing core having a plurality of sub cores;
a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core; and
a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device, wherein each of the cells comprises:
a floating gate structure; and
a plurality of diffusion breaks along an extent of the cell.

6. The semiconductor device of claim 5 , wherein each of the cells has a width of three grid units or less.

7. The semiconductor device of claim 5 , wherein the first sub core and the second sub core are in separate power domains, and wherein the separate power domains correspond to separate power supplies.

8. The semiconductor device of claim 5 , further comprising:
an additional power rail perpendicular to the plurality of power rails and coupled with the plurality of power rails within the first sub core; and
an additional cell providing a discontinuity in the additional power rail.

9. A semiconductor chip comprising:
a plurality of processing cores disposed within semiconductor material of the semiconductor chip, a first one of the processing cores having a first sub core and a second sub core;
a power rail spanning from the first sub core to the second sub core, the power rail including conductive lines within the semiconductor material; and
a cell abutting the first sub core and the second sub core on the power rail, the cell providing a discontinuity in the power rail at a plurality of metal layers of the conductive lines;
an additional power rail perpendicular to the power rail and in communication with the power rail within the first sub core; and
an additional cell providing a discontinuity in the additional power rail.

10. The semiconductor chip of claim 9 , wherein the cell comprises:
a first power source (VDD) contact; and
a second VDD contact, the first and second VDD contacts being built within a common N-type doped region of a substrate of the semiconductor chip.

11. The semiconductor chip of claim 10 , wherein the first VDD contact is coupled to the power rail at the first sub core, and wherein the second VDD contact is coupled to the power rail at the second sub core.

12. The semiconductor chip of claim 10 , wherein the first VDD contact and the second VDD contact are not directly coupled with doped semiconductor material of the N-type doped region.

13. The semiconductor chip of claim 9 , wherein the power rail includes a conductive line for ground (VSS) and a conductive line for VDD, wherein the conductive line for VSS runs continuously through the cell.

14. The semiconductor chip of claim 9 , wherein the first sub core and the second sub core are in separate power domains.

15. The semiconductor chip of claim 9 , wherein the cell comprises:
a gate structure disposed on a substrate of the semiconductor chip and not associated with a transistor.

16. A semiconductor chip having a processing core, the processing core comprising:
a first sub core;
a second sub core;
means for distributing power to the first sub core and the second sub core; and
means for providing discontinuities in the power distributing means at multiple metal layers of the semiconductor chip, wherein a boundary between the first sub core and the second sub core is defined by the discontinuity providing means abutting the first sub core and the second sub core, wherein the processing core comprises a Graphics Processing Unit (GPU), and wherein the first sub core comprises a shader unit, and wherein the second sub core comprises an accumulator unit.

17. The semiconductor chip of claim 16 , wherein the discontinuity providing means includes a plurality of cells at the boundary, wherein each of the cells comprises:
a first power source (VDD) contact; and
a second VDD contact, the first and second VDD contacts being built within a common N-type doped region of a substrate of the semiconductor chip.

18. The semiconductor chip of claim 17 , wherein the first VDD contact is coupled to a respective power rail on a side of the boundary corresponding to the first sub core, and wherein the second VDD contact is coupled to the respective power rail on a side of the boundary corresponding to the second sub core.

19. The semiconductor chip of claim 17 , wherein the first VDD contact and the second VDD contact are not directly coupled with doped semiconductor material of the N-type doped region.

20. The semiconductor chip of claim 16 , wherein the power distributing means comprise a plurality of power rails, and wherein the discontinuity providing means comprise a plurality of cells defining the boundary at points where the power rails span from the first sub core to the second sub core.

21. The semiconductor chip of claim 20 , wherein each power rail includes a conductive line for ground (VSS) and a conductive line for power source (VDD) VDD, wherein the conductive lines for VSS do not include discontinuities provided by the cells.

22. The semiconductor chip of claim 16 , wherein the first sub core and the second sub core are in separate power domains, and further wherein the separate power domains correspond to separate power supplies.

Assignees

• Qualcomm Inc

Inventors

• Sahu Satyanarayana
• Raj Satish
• Chandrasekaran Shiva Ram
• Qiu Li
• Tyagi Arun
• Philip Mathew
• Verma Rajesh

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• H10P72/0612

  Production flow monitoring, e.g. for increasing throughput · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title