Redistribution layer structure, semiconductor substrate structure, semiconductor package structure, chip structure, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9955590-B2
Application number	US-201514919343-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 21, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

The present disclosure relates to redistribution layer structures useful in semiconductor substrate packages, semiconductor package structures, and chip structures. In an embodiment, a redistribution layer structure includes a dielectric layer, an anti-plating layer, and a conductive material. The dielectric layer defines one or more trenches. The conductive material is disposed in the trench(es), and the anti-plating layer is disposed on a surface of the dielectric layer.

First claim

What is claimed is:

1. A redistribution layer structure, comprising:
a dielectric layer comprising an upper portion and a lower portion, the lower portion of the dielectric layer defining at least one trench, and the upper portion of the dielectric layer comprising an anti-plating layer disposed on a surface of the lower portion of the dielectric layer and defining an opening; and
a conductive material plated in the trench within the opening,
wherein the anti-plating layer does not extend over the trench, the anti-plating layer includes a hydrophobic material, and the lower portion of the dielectric layer defining the trench is hydrophilic.

2. The redistribution layer structure of claim 1 , wherein the anti-plating layer is disposed on the surface of the lower portion of the dielectric layer and not in the trench.

3. The redistribution layer structure of claim 1 , wherein the dielectric layer includes one of polyimide or epoxy.

4. The redistribution layer structure of claim 1 , wherein a cross-section of the trench is in V-shape.

5. The redistribution layer structure of claim 1 , wherein the anti-plating layer includes a material selected from a group consisting of silicon dioxide, silicon nitride, parylene-N, parylene-C, parylene-D, parylene-AF4, and a mixture thereof.

6. The redistribution layer structure of claim 1 , wherein the anti-plating layer includes a first layer and a second layer, the first layer is selected from a group consisting of silicon dioxide, silicon nitride, and a combination thereof, and the second layer is selected from a group consisting of parylene-N, parylene-C, parylene-D, parylene-AF4, and a combination thereof.

7. The redistribution layer structure of claim 1 , wherein a portion of the conductive material is disposed on at least a portion of the anti-plating layer.

8. The redistribution layer structure of claim 1 , wherein the trench extends through the lower portion of the dielectric layer.

9. The redistribution layer structure of claim 8 , wherein the trench includes an upper portion and a lower portion, and the lower portion of the trench is filled with an interconnection metal.

10. The redistribution layer structure of claim 9 , wherein the conductive material covers and contacts the interconnection metal.

11. The redistribution layer structure of claim 1 , further comprising a protection layer disposed on the anti-plating layer, wherein the protection layer defines an opening to expose the conductive material.

12. A redistribution layer structure, comprising:
a dielectric layer comprising an upper portion and a lower portion, the lower portion of the dielectric layer defining at least one trench, and the upper portion of the dielectric layer comprising an anti-plating layer disposed on a surface of the lower portion of the dielectric layer and defining an opening; and
a conductive material plated in the trench within the opening, wherein a portion of the anti-plating layer is disposed on a side surface of the trench.

13. The redistribution layer structure of claim 12 , wherein the conductive material includes a material selected from a group consisting of palladium, copper and nickel.

Assignees

• Advanced Semiconductor Eng

Inventors

• Weng Chao-Fu

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title