Out of plane structures and methods for making out of plane structures

Patent metadata

Field	Value
Publication number	US-9955575-B1
Application number	US-201715651311-A
Country	US
Kind code	B1
Filing date	Jul 17, 2017
Priority date	Jul 17, 2017
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A three dimensional device comprises a substrate and a film comprising one or more stress engineered layers. The film includes elastic portions that are curled out of plane with respect to the substrate and anchor portions that attach the elastic portions and to the substrate. An outer conductive layer is disposed over the elastic portions and the anchor portions. The device includes one or more electrically conductive stubs that extend between two adjacent anchor portions without electrically connecting the two adjacent anchor portions.

First claim

The invention claimed is:

1. A device comprising:
a substrate;
a film comprising one or more stress engineered layers, the film comprising:
elastic portions that are curled out of plane with respect to the substrate; and
anchor portions that attach the elastic portions and to the substrate;

an outer conductive layer disposed over the elastic portions and the anchor portions; and
one or more electrically conductive stubs that extend between two adjacent anchor portions without electrically connecting the two adjacent anchor portions.

2. The device of claim 1 , further comprising a photoresist artifact disposed on the substrate between the anchor portions.

3. The device of claim 1 , wherein the stubs are electroplated remnants of a release layer for the elastic portions.

4. The device of claim 3 , wherein the stubs bend away from the anchor portions.

5. A circuit system comprising:
a circuit substrate;
one or more electronic components disposed on the circuit substrate;
an electrically conductive three dimensional structure electrically connected to at least one of the electronic components, the three dimensional structure comprising:
a film comprising one or more stress engineered layers, the film comprising:
elastic portions curled into a three dimensional shape; and
anchor portions attached to the elastic portions; and

an outer conductive layer disposed over the elastic portions and the anchor portions; and

one or more conductive stubs that extend between two adjacent anchor portions without electrically connecting the two adjacent anchor portions.

6. The system of claim 5 , further comprising one or more dielectric interlayers disposed between the three dimensional structure and the circuit substrate.

7. The system of claim 6 , wherein the one or more dielectric interlayers include:
a first dielectric interlayer disposed on the circuit substrate; and
a second dielectric interlayer; and
further comprising:
electrically conductive traces routed between one or both of the first interlayer dielectric and the second interlayer dielectric, the electrically conductive traces electrically connecting at least one of the electronic components to the three dimensional structure.

8. A method for forming a three dimensional structure comprising:
depositing a stress engineered film over a conductive layer, the stress engineered film including:
elastic portions having a non-uniform stress profile through the thickness of the one or more layers such that the stress engineered film curls when released from the conductive layer; and
anchor portions configured to remain attached to the conductive layer;

forming gaps in the conductive layer between neighboring anchor portions;
depositing a mask layer defining one or more release windows;
etching the conductive layer in the release windows, the etching releasing the elastic portions of the stress engineered film such that the elastic portions curl to form the three dimensional structure; and
electroplating the three dimensional structure using the conductive layer as a contact for the electroplating.

9. The method of claim 8 , wherein depositing the mask layer comprises depositing mask material within the gaps.

10. The method of claim 9 , wherein the mask material substantially fills the gaps in the conductive layer.

11. The method of claim 8 , wherein the elastic portions of the stress engineered film curl to form three dimensional coil loops.

12. The method of claim 11 , wherein the three dimensional coil loops form loops of a three dimensional inductor.

13. The method of claim 8 , further comprising forming load elements on the elastic portions.

14. The method of claim 13 , further comprising removing the load elements after releasing the elastic portions.

15. The method of claim 13 , further comprising heating the three dimensional structure after releasing the elastic portions.

16. The method of claim 15 , wherein the heating softens the load elements and controls the curling of the elastic portions during the heating.

17. The method of claim 15 , wherein heating the three dimensional structures comprises heating at less than about 120 degrees C.

18. The method of claim 8 , wherein the curling of the elastic portions comprises engaging interlocking features disposed at tips of the elastic portions.

19. The method of claim 8 , wherein the gaps extend at least 50% of a distance between the neighboring anchor portions.

20. The method of claim 8 , wherein the gaps extend at least 50% of a length of the anchor portions.

21. The method of claim 8 , wherein a distance between neighboring anchor portions is less than about 100 μm.

22. The method of claim 8 further including removing the mask layer after the electroplating.

23. The method of claim 22 further including removing the conductive layer after removing the mask layer.

Assignees

• Palo Alto Res Ct Inc

Inventors

• Wang Yu
• Chua Christopher L
• Wang Qian

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H05K1/0393 Primary

  Flexible materials (H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups) · CPC title

• H01F27/2828

  Construction of conductive connections, of leads · CPC title

• H05K1/11

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K1/165

  incorporating printed inductors · CPC title