Method and devices for reducing peak to average power ratio

Patent metadata

Field	Value
Publication number	US-9954707-B2
Application number	US-201615391183-A
Country	US
Kind code	B2
Filing date	Dec 27, 2016
Priority date	Dec 28, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

According to an aspect of the inventive concept, there is provided a crest factor reduction (CFR) core, including: a clipper clipping an input signal; a delay unit delaying the input signal; a first subtractor subtracting the clipped input signal from the delayed input signal; an error shaping filter filtering the subtracted signal for shaping an error which occurs by the clipping of the input signal; a digital filter filtering the input signal for cancelling noise of the input signal; and a second subtractor subtracting the filtered subtracted signal from the filtered input signal.

First claim

What is claimed is:

1. A crest factor reduction (CFR) core comprising:
a clipper clipping an input signal;
a delay unit delaying the input signal;
a first subtractor subtracting the clipped input signal from the delayed input signal;
an error shaping filter filtering the subtracted signal for shaping an error which occurs by the clipping of the input signal;
a digital filter filtering the input signal for cancelling noise of the input signal; and
a second subtractor subtracting the filtered subtracted signal from the filtered input signal.

2. The CFR core of claim 1 , wherein a time required for filtering the input signal is substantially equivalent to an aggregation time of a time required for delaying the input signal, a time required for subtracting the clipped input signal from the delayed input signal, and a time required for filtering the subtracted signal.

3. The CFR core of claim 1 , wherein the error shaping filter is a finite impulse response (FIR) filter.

4. The CFR core of claim 1 , wherein the digital filter is the finite impulse response (FIR) filter.

5. A repeater comprising:
a first antenna receiving a first analog signal;
an analog to digital converter (ADC) converting the first analog signal into a first digital signal;
a CFR core receiving the first digital signal and outputting the received first digital signal as a second digital signal having a reduced PAPR;
a digital to analog converter (DAC) converting the second digital signal into a second analog signal; and
a second antenna transmitting the second analog signal,
wherein the CFR core includes
a clipper clipping the first digital signal;
a delay unit delaying the first digital signal;
a first subtractor subtracting the clipped first digital signal from the delayed first digital signal;
an error shaping filter filtering the subtracted signal for shaping an error which occurs by the clipping of the first digital signal;
a digital filter filtering the first digital signal for cancelling noise of the first digital signal; and
a second subtractor subtracting the filtered subtracted signal from the filtered first digital signal.

6. The repeater of claim 5 , wherein a time required for filtering the first digital signal is substantially equivalent to an aggregation time of a time required for delaying the first digital signal, a time required for subtracting the clipped first digital signal from the first digital signal, and a time required for filtering the subtracted signal.

7. The repeater of claim 5 , wherein the error shaping filter is an FIR filter.

8. A method for reducing a PAPR, the method comprising:
clipping an input signal;
delaying the input signal;
subtracting the clipped input signal from the delayed input signal;
filtering the subtracted signal for shaping an error which occurs by the clipping of the input signal;
filtering the input signal for cancelling noise of the input signal; and
subtracting the filtered subtracted signal from the filtered input signal.

9. The method of claim 8 , wherein a time required for filtering the input signal is substantially equivalent to an aggregation time of a time required for delaying the input signal, a time required for subtracting the clipped input signal from the delayed input signal, and a time required for filtering the subtracted signal.

10. The method of claim 8 , wherein a level of the clipped input signal is a threshold value or less.

Assignees

• Solid Inc

Inventors

• KWON Nagwon
• Kim Hyunchae

Classifications

• H04L27/2624

  by soft clipping · CPC title

• H04B7/15 Primary

  Active relay systems · CPC title

• H04L27/2623 Primary

  Reduction thereof by clipping · CPC title

• H04W52/36

  with a discrete range or set of values, e.g. step size, ramping or offsets · CPC title