Frame bit detector in near field communications

US9954670B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9954670-B2
Application numberUS-201514753616-A
CountryUS
Kind codeB2
Filing dateJun 29, 2015
Priority dateJun 29, 2015
Publication dateApr 24, 2018
Grant dateApr 24, 2018

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Abstract

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Described herein are architectures, platforms and methods for (NFC) frame bit detection. A frame bit detector includes a sample-based bit detector that receives samples which may be data and non-data (noise), identifies data bits at every sample input time, and the likelihoods that the identified data bits are part of data. The frame detector includes a maximum likelihood frame detector configured to receive bits from the sample-based bit detector and the likelihood of each bit that the bit is data, and calculate frame likelihood.

First claim

Opening claim text (preview).

What is claimed is: 1. A near field communication (NFC) enabled device, comprising: an NFC receiver comprising a frame bit detector comprised of: a sample-based bit detector configured to receive demodulated samples obtained from data and non-data, identify data bits at every sample input time, and the likelihoods that the identified data bits are part of data; and a maximum likelihood frame detector configured to receive bits from the sample-based bit detector and the likelihood of each bit that the bit is data, and calculate frame likelihood. 2. The NFC enabled device of claim 1 , wherein the sample-based bit detector is configured to output all possible results of all received bits at every sample input time, independent of whether the received bits are data or non-data. 3. The NFC enabled device of claim 1 , wherein the sample-based bit detector is configured to calculate bit likelihood based on bit decision error which is a minimum distance to a point in a constellation of bits. 4. The NFC enabled device of claim 1 , wherein the sample-based bit detector is configured to calculate the value of a bit through a slicer, with an input quantity computed by received samples in a bit duration based on a bit coding scheme. 5. The NFC enabled device of claim 4 , wherein the sample-based bit detector is configured to compute the input quantity to the slicer which is modified from a previous input quantity with current input sample before the signal of frame arrival is not valid. 6. The NFC enabled device of claim 1 , wherein the maximum likelihood frame detector is configured to identify full frame or partial frame at every bit arrival from the sample-based bit detector. 7. The NFC enabled device of claim 1 , wherein the maximum likelihood frame detector is configured to calculate frame likelihood by a moving sum of the bit likelihoods of detected data bits sharing a same bit boundary timing. 8. The NFC enabled device of claim 1 , wherein the maximum likelihood detector is further configured to identify frame arrival based on a number of bit likelihoods larger than an average (AVG) value that is estimated when no communication is conducted or given by other software and hardware modules. 9. The NFC enabled device of claim 1 , wherein the maximum likelihood detector is further configured to feedback a signal of frame arrival to sample-based bit detector after frame arrival is identified. 10. The NFC enabled device of claim 1 , wherein the sample-based bit detector is further configured to use signal of frame arrival to reduce power consumption by detecting a bit at the arrival of the last sample of the bit, wherein the last sample of a bit is identified by the timing of a signal of frame arrival.

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Classifications

  • Electricity · mapped topic

  • in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems · CPC title

  • by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

  • H04L1/0054Primary

    Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms · CPC title

  • H04L7/0016Primary

    correction of synchronization errors · CPC title

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What does patent US9954670B2 cover?
Described herein are architectures, platforms and methods for (NFC) frame bit detection. A frame bit detector includes a sample-based bit detector that receives samples which may be data and non-data (noise), identifies data bits at every sample input time, and the likelihoods that the identified data bits are part of data. The frame detector includes a maximum likelihood frame detector configu…
Who is the assignee on this patent?
Intel Ip Corp
What technology area does this patent fall under?
Primary CPC classification H04L1/0054. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 24 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).