Variable width error correction

Patent metadata

Field	Value
Publication number	US-9954557-B2
Application number	US-201414265907-A
Country	US
Kind code	B2
Filing date	Apr 30, 2014
Priority date	Apr 30, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Variable width error correction is described. A memory controller can determine, from a memory address, what type of error correction is to be applied for the address region of that memory address and can generate commands for the memory device. An amount of error correction metadata associated with that address region may vary depending on the spatial location of the address region. In some cases, two translations may be performed: one by a processor using information set up by an operating system and another by the memory controller (or the memory device). In other cases, a single translation may be performed, for example by a processor using information set up by the operating system, which can determine the variable error correction during translation of a virtual address region to a real physical address region.

First claim

What is claimed is:

1. A memory controller, comprising:
a translation module that translates expected physical memory addresses having fixed sized address regions to real physical memory addresses having varying sized address regions, wherein the varying sized address regions are tied to spatially distinct regions of memory having similar expected or experienced weakness to succumbing to memory errors;
wherein the translation module:
receives an expected physical memory address;
performs a look up of a real physical address for the expected physical memory address; and
performs a look up of an error correction attribute of the corresponding real physical memory address, wherein the error correction attribute comprises an indication of a number of cycles to service a read request to the corresponding real physical memory address, wherein the number of cycles assigned to each spatially distinct region of memory are dependent on a determined error correction requirement; and

control logic that issues commands to at least one memory device according to the real physical address identified by the translation module, wherein the commands comprise a row command and a column command based on the real physical memory address, and a cycle command based on the number of cycles indicated by the error correction attribute.

2. The memory controller of claim 1 , further comprising a storage system providing registers for the memory controller and storing organized information corresponding to error correction attributes for the real physical memory addresses, wherein the translation module performs the look up of the error correction attribute in the storage system.

3. The memory controller of claim 2 , wherein the organized information is generated by testing the at least one memory device for spatially clustered weaknesses, the memory controller being configured to generate the organized information upon specified conditions.

4. The memory controller of claim 3 , wherein the specified conditions comprise at least one of a boot condition, a run-time based condition, and a time sensitive condition.

5. The memory controller of claim 1 , wherein the cycle command is embedded in one or both of the row command and the column command.

6. A memory controller, comprising:
a translation module that translates expected physical memory addresses having fixed sized address regions to real physical memory addresses having varying sized address regions, wherein the varying sized address regions are tied to spatially distinct regions of memory having similar expected or experienced weakness to succumbing to memory errors;
wherein the translation module:
receives an expected physical memory address; and
performs a look up of a real physical address for the expected physical memory address; and

control logic that issues commands to at least one memory device according to the real physical address identified by the translation module,
wherein the real physical memory addresses store interleaved data and error correction metadata, and include aligned memory addresses and unaligned memory addresses,
wherein for a read request to an expected physical memory address translated by the translation module to an unaligned memory address, the control logic issues, as part of a same read request, commands comprising a first row activation command, a first column command, a second row activation command and a second column command.

7. A memory controller comprising hardware and configured to:
associate error correction requirements with physical regions containing memory cells or blocks of a memory module that have similar expected or experienced weakness to succumbing to memory errors and that are spatially clustered;
determine, for a real physical memory address, an error correction requirement based on which physical region of the physical regions that memory cells or blocks addressed by the real physical memory address belongs; and
send a command to the memory module based on the error correction requirement, wherein the error correction requirement comprises a number of cycles to service a read request for the memory module, the command comprising a cycle command based on the number of cycles indicated by the error correction requirement.

8. The memory controller of claim 7 , wherein the memory controller is further configured to perform error correction on data received from the memory module as a result of the command according to the error correction requirement.

9. The memory controller of claim 7 , wherein the memory controller is further configured to:
receive a request comprising an expected memory address; and
perform a translation from the expected memory address to the real physical memory address, wherein the command to the memory module corresponds to the request.

10. The memory controller of claim 7 , wherein the memory controller is further configured to test the memory module for spatially clustered weaknesses of physical regions of the memory module and generate error correction attributes for the real physical memory addresses to the physical regions of the memory module.

Assignees

• Microsoft Corp
• Microsoft Technology Licensing Llc

Inventors

• Glaskowsky Peter
• Strauss Karin

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03M13/35 Primary

  Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics · CPC title

• G06F12/04

  Addressing variable-length words or parts of words · CPC title

• G06F11/0796 Primary

  Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element · CPC title