Circuits for low noise amplifiers with interferer reflecting loops

US9954497B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9954497-B2
Application numberUS-201515117662-A
CountryUS
Kind codeB2
Filing dateFeb 9, 2015
Priority dateFeb 9, 2014
Publication dateApr 24, 2018
Grant dateApr 24, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Circuits for low noise amplifiers with interferer reflecting loops are provided. In some embodiments, circuits for a low noise amplifier with an interferer reflecting loop are provided, the circuits comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit for a low noise amplifier with an interferer reflecting loop, comprising: a low noise amplifier (LNA) having an input and an output, comprising: a common gate transconductor having an input coupled to the input of the LNA and an output; a common source transconductor having an input coupled to the input of the LNA and an output; a first radio frequency trans-impedance amplifier (RF-TIA) having an input coupled to the output of the common gate transconductor and having an output coupled to the output of the LNA; and a second RF-TIA having an input couple to the output of the common source transconductor and having an output coupled to the output of the LNA; a buffer having an input coupled to the output of the LNA and an output; and a notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA. 2. The circuit of claim 1 , wherein LNA is a wideband LNA. 3. The circuit of claim 1 , where a gain of the LNA can be changed in the field. 4. The circuit of claim 1 , wherein the common source transconductor is a multi-slice common source transconductor. 5. The circuit of claim 4 , wherein each slice of the multi-slice common source transconductor is switchable. 6. The circuit of claim 1 , wherein the second RF-TIA is a multi-slice RF-TIA. 7. The circuit of claim 6 , wherein each slice of the multi-slice RF-TIA is switchable. 8. The circuit of claim 1 , wherein a ratio of a contribution of an output signal of the first RF-TIA to an output signal of the second RF-TIA in the output of the LNA is controllable in the field. 9. The circuit of claim 1 , wherein the buffer comprises a class-AB complementary source follower. 10. The circuit of claim 1 , wherein the notch filter is a switched-capacitor N-path notch filter. 11. The circuit of claim 10 , wherein the notch filter comprises: a first terminal; a second terminal; a plurality of capacitors each having a first side and a second side; and a plurality of switches each having a first side and a second side, wherein the first side of each of a first half of the plurality of switches are connected to the first terminal, the second side of each of the first half of the plurality of switches are connected to the first side of each of two unique ones of the plurality of capacitors, the first side of each of a second half of the plurality of switches are connected to the second terminal, and the second side of each of the second half of the plurality of switches are connected to the second side of each of two unique ones of the plurality of capacitors. 12. The circuit of claim 11 , wherein the plurality of switches are formed from transistors. 13. The circuit of claim 11 , wherein a multiphase clock signal controls the plurality of switches. 14. The circuit of claim 13 , further comprising a divide-by-four, dual-edge-triggered latch divider and a plurality of NAND gates to create the multiphase clock signal. 15. The circuit of claim 1 , wherein the notch filter comprises switchable capacitors and a spiral inductor. 16. The circuit of claim 1 , wherein the notch filter comprises switchable capacitors and an inductor formed from bondwires. 17. A circuit for a low noise amplifier with an interferer reflecting loop, comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and a notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA, wherein the notch filter is a switched-capacitor N-path notch filter comprising: a first terminal; a second terminal; a plurality of capacitors each having a first side and a second side; and a plurality of switches each having a first side and a second side, wherein the first side of each of a first half of the plurality of switches are connected to the first terminal, the second side of each of the first half of the plurality of switches are connected to the first side of each of two unique ones of the plurality of capacitors, the first side of each of a second half of the plurality of switches are connected to the second terminal, and the second side of each of the second half of the plurality of switches are connected to the second side of each of two unique ones of the plurality of capacitors. 18. The circuit of claim 17 , wherein LNA is a wideband LNA. 19. The circuit of claim 17 , where a gain of the LNA can be changed in the field. 20. The circuit of claim 17 , wherein: the LNA comprises: a common gate transconductor having an input coupled to the input of the LNA and an output; a common source transconductor having an input coupled to the input of the LNA and an output; a first radio frequency trans-impedance amplifier (RF-TIA) having an input coupled to the output of the common gate transconductor and having an output coupled to the output of the LNA; and a second RF-TIA having an input couple to the output of the common source transconductor and having an output coupled to the output of the LNA; and the common source transconductor is a multi-slice common source transconductor. 21. The circuit of claim 20 , wherein each slice of the multi-slice common source transconductor is switchable. 22. The circuit of claim 17 , wherein: the LNA comprises: a common gate transconductor having an input coupled to the input of the LNA and an output; a common source transconductor having an input coupled to the input of the LNA and an output; a first radio frequency trans-impedance amplifier (RF-TIA) having an input coupled to the output of the common gate transconductor and having an output coupled to the output of the LNA; and a second RF-TIA having an input couple to the output of the common source transconductor and having an output coupled to the output of the LNA; and the second RF-TIA is a multi-slice RF-TIA. 23. The circuit of claim 22 , wherein each slice of the multi-slice RF-TIA is switchable. 24. The circuit of claim 17 , wherein: the LNA comprises: a common gate transconductor having an input coupled to the input of the LNA and an output; a common source transconductor having an input coupled to the input of the LNA and an output; a first radio frequency trans-impedance amplifier (RF-TIA) having an input coupled to the output of the common gate transconductor and having an output coupled to the output of the LNA; and a second RF-TIA having an input couple to the output of the common source transconductor and having an output coupled to the output of the LNA; and a ratio of a contribution of an output signal of the first RF-TIA to an output signal of the second RF-TIA in the output of the LNA is controllable in the field. 25. The circuit of claim 17 , wherein the buffer comprises a class-AB complementary source follower. 26. The circuit of claim 17 , wherein the plurality of switches are formed from transistors. 27. The circuit of claim 17 , wherein a multiphase clock signal controls the plurality of switches. 28. The circuit of claim 27 , further comprising a divide-by-four, dual-edge-triggered latch divider and a plurality of NAND gates to create the multiphase clock signal. 29. The circuit of claim 17 , wherein the notch filter comprises switchable capacitors and a spiral inductor.

Assignees

Inventors

Classifications

  • the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC · CPC title

  • A balun, i.e. balanced to or from unbalanced converter, being present at the input of an amplifier · CPC title

  • A balun, i.e. balanced to or from unbalanced converter, being present at the output of an amplifier · CPC title

  • using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

  • using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9954497B2 cover?
Circuits for low noise amplifiers with interferer reflecting loops are provided. In some embodiments, circuits for a low noise amplifier with an interferer reflecting loop are provided, the circuits comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and notch filter having an input coupled to the output…
Who is the assignee on this patent?
Univ Columbia
What technology area does this patent fall under?
Primary CPC classification H03F1/342. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 24 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).