Mitigating amplifier pop noise

Patent metadata

Field	Value
Publication number	US-9954496-B2
Application number	US-201615385200-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Dec 21, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.

First claim

What is claimed is:

1. A system, comprising:
an amplifier containing a first bias current source and configured to provide an output voltage at a node;
a gain stage coupled to the node and comprising a second bias current source;
a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load; and
a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.

2. The system of claim 1 , further comprising an offset compensation circuit coupled to the node and to the amplifier, the offset compensation circuit configured to compensate an offset voltage introduced to the node by one or more transistors in the buffer stage.

3. The system of claim 2 , wherein the amplifier and the offset compensation circuit maintain the output voltage at the node at ground when the controller activates the third and fourth bias current sources.

4. The system of claim 2 , wherein the offset compensation circuit comprises one or more additional bias current sources and one or more additional transistors, and wherein emitter areas of the one or more additional transistors and currents provided by the one or more additional bias current sources result in the same current densities in the one or more additional transistors as the current densities in the one or more transistors in the buffer stage.

5. The system of claim 1 , wherein the controller is further configured to deactivate the first bias current source after the third and fourth bias current sources are activated.

6. The system of claim 1 , wherein the controller is further configured to close one or more switches in the amplifier to preclude the amplifier from applying a voltage or a current to the node.

7. The system of claim 1 , wherein the buffer stage couples to an audio output jack of a mobile electronic device.

8. The system of claim 1 , wherein the amplifier comprises multiple current mirrors.

9. The system of claim 1 , wherein the buffer stage includes an NPN transistor stack coupled to the third bias current source and a PNP transistor stack coupled to the fourth bias current source, the third and fourth bias current sources and the NPN and PNP transistor stacks configured to keep each of the output transistors in the buffer stage on when the other transistor in the pair is channeling current.

10. A system, comprising:
an amplifier comprising a first bias current source coupled to multiple current mirrors, a node of the amplifier positioned between first and second transistors of the amplifier and configured to provide current to the node, the amplifier further comprising multiple switches configured to regulate current flow through the first and second transistors;
an offset compensation circuit, coupled to the amplifier, that includes second and third bias current sources and third and fourth transistors, the second and third bias current sources and the third and fourth transistors configured to reduce an offset voltage applied to the node;
a gain stage coupled to the node; and
a buffer stage coupled to the node and comprising a fourth bias current source coupled to an emitter of a fifth transistor, a fifth bias current source coupled to an emitter of a sixth transistor, a sixth bias current source coupled to a collector of a seventh transistor, a seventh bias current source coupled to a collector of an eighth transistor, the buffer stage further comprising a ninth transistor having a base coupled to the sixth bias current source and a tenth transistor having another base coupled to the seventh bias current source, the collectors of the ninth and tenth transistors configured to couple to an audio device load,
wherein the buffer stage further comprises an eighth bias current source coupled to an NPN transistor stack and to an eleventh transistor, an emitter of the eleventh transistor coupled to the base of the tenth transistor, and wherein the buffer stage further includes a ninth bias current source coupled to a PNP transistor stack and to a twelfth transistor, an emitter of the twelfth transistor coupled to the base of the ninth transistor.

11. The system of claim 10 , wherein the offset compensation circuit is positioned in a feedback loop of the amplifier.

12. The system of claim 10 , wherein each of the eighth and ninth bias current sources is configured to provide more current than each of the fourth, fifth, sixth, and seventh bias current sources.

13. The system of claim 10 , further comprising a controller configured to:
activate the first, second, and third bias current sources;
activate the fourth, fifth, sixth, and seventh bias current sources after the first, second, and third bias current sources have been activated; and
activate the eighth and ninth bias current sources after the fourth, fifth, sixth, and seventh bias current sources have been activated.

14. The system of claim 13 , wherein the controller is configured to preclude the amplifier from affecting a voltage at the node after the eighth and ninth bias current sources have been activated.

15. The system of claim 10 , wherein the controller is configured to:
deactivate the eighth and ninth bias current sources;
deactivate the fourth, fifth, sixth, and seventh bias current sources after the eighth and ninth bias current sources have been deactivated; and
deactivate the first, second, and third bias current sources after the fourth, fifth, sixth, and seventh bias current sources have been deactivated.

16. The system of claim 10 , wherein the third and fourth transistors in the offset compensation circuit include NPN and PNP transistors, wherein the fifth, seventh, and tenth transistors are NPN transistors, and wherein the sixth, eighth, and ninth transistors are PNP transistors.

17. A method, comprising:
activating an amplifier bias current in an amplifier and an offset compensation bias current in an offset compensation circuit;
holding a voltage at an output node of the amplifier within a predetermined range from ground;
activating a gain stage bias current and first and second pairs of buffer stage bias currents after activating the amplifier bias current and the offset compensation bias current;
holding an output voltage of the buffer stage within the predetermined range from ground; and
activating a third pair of buffer stage bias currents after activating the gain stage bias current and the first and second pairs of buffer stage bias currents and while the output voltage of the buffer stage is within the predetermined range from ground.

18. The method of claim 17 , further comprising deactivating the amplifier after activating the third pair of buffer stage bias currents.

19. The method of claim 17 , further comprising deactivating the third pair of buffer stage bias currents, then deactivating the gain stage bias current and the first and second pairs of buffer stage bias currents, then deactivating the amplifier bias current and the offset compensation bias current.

20. The method of claim 17 , furthe

Assignees

• Texas Instruments Inc

Inventors

• Brantley Steven G
• Vasan Bharath Karthik
• Caldwell John Lawrence

Classifications

• H03G1/0023

  in emitter-coupled or cascode amplifiers (H03G1/0029 takes precedence) · CPC title

• H03F2200/375

  Circuitry to compensate the offset being present in an amplifier · CPC title

• H03F3/187

  in integrated circuits · CPC title

• H03G3/3005

  in amplifiers suitable for low-frequencies, e.g. audio amplifiers (H03G3/32, H03G3/34 take precedence) · CPC title

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title