Electronic device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9954171-B2
Application number	US-201414484295-A
Country	US
Kind code	B2
Filing date	Sep 12, 2014
Priority date	Apr 7, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A manufacturing method of an electronic device includes: providing a substrate; forming a source and a drain on the substrate; forming a semiconductor layer on the substrate; forming a first light sensitive material layer on the semiconductor layer; removing a first portion of the first light sensitive material layer by a first exposure and development process and maintaining a second portion of the first light sensitive material layer to serve as a first gate insulation layer; patterning the semiconductor layer to form a channel layer below the first gate insulation layer; forming a second light sensitive material layer on the substrate; removing a third portion of the second light sensitive material layer by a second exposure and development process to expose at least a part of the first gate insulation layer; and forming a first gate on the first gate insulation layer. An electronic device is also provided.

First claim

What is claimed is:

1. An electronic device, comprising:
a substrate;
a source, disposed on the substrate;
a drain, disposed on the substrate;
a channel layer, connecting the source and the drain;
a first gate insulation layer, disposed on the channel layer;
a dielectric layer, covering a portion of the substrate and exposing at least a portion of the first gate insulation layer; and
a first gate, disposed on the first gate insulation layer,
wherein the first gate insulation layer has a first end and a second end opposite to each other, and the first end and the second end are respectively perpendicular to a surface of the substrate, an orthogonal projection of the first end onto the substrate is on an orthogonal projection of the source onto the substrate, and an orthogonal projection of the second end onto the substrate is on an orthogonal projection of the drain onto the substrate, the source and the drain respectively have a side perpendicular to the surface of the substrate, and the first end and the second end are respectively aligned with the side of the source and the side of the drain,
wherein one of two opposite ends of the channel layer is aligned to the first end of the first gate insulation layer, and the other one of the two opposite ends of the channel layer is aligned to the second end of the first gate insulation layer.

2. The electronic device as claimed in claim 1 , wherein the first gate insulation layer and the dielectric layer are formed of a material originating from a light sensitive material capable of being removed in an exposure and development process, and the light sensitive material comprises polyvinylphenol (PVP), polyvinyl alcohol (PVA), phase transfer photoresist, or negative photoresist.

3. The electronic device as claimed in claim 1 , wherein a material of the channel layer is an organic semiconductor or a metal oxide semiconductor.

4. The electronic device as claimed in claim 1 , wherein a material of the channel layer comprises pentacene, poly(3-hexylthiophene) (P3HT), poly(3.3′″-didodecylquarterthiophene) (PQT-12), or indium gallium zinc oxide.

5. The electronic device as claimed in claim 1 , further comprising:
a second gate, disposed between the channel layer and the substrate; and
a second gate insulation layer, disposed on the substrate, covering the second gate, and located between the second gate and the channel layer.

6. The electronic device as claimed in claim 1 , further comprising:
a patterned inter-layer intermediate layer, disposed on the dielectric layer, covering the first gate, and exposing the drain; and
a pixel electrode, disposed on the patterned inter-layer intermediate layer and being connected with the drain.

7. The electronic device as claimed in claim 1 , further comprising:
a capacitor insulation layer, covering a portion of the drain; and
a capacitor electrode, disposed on the capacitor insulation layer, wherein the capacitor electrode, the capacitor insulation layer, and the drain form a capacitor.

8. The electronic device as claimed in claim 7 , wherein an orthogonal projection of the capacitor electrode onto the substrate is on an orthogonal projection of the drain onto the substrate.

9. The electronic device as claimed in claim 1 , wherein the dielectric layer has an opening exposing at least a portion of the first gate insulation layer, and a range of distribution of the opening in a direction parallel to an arrangement of the source and the drain is from a first range of distribution to a second range of distribution, wherein the first range of distribution is from a position aligned with the side of the source toward the drain to a position aligned with the side of the drain toward the source, and the second range of distribution is from a position aligned with another side of the source away from the drain to a position aligned with another side of the drain away from the source.

10. The electronic device as claimed in claim 1 , wherein materials of the source, the drain, and the first gate are a metal, an alloy thereof, a metal oxide, or an organic conductive material.

11. The electronic device as claimed in claim 1 , wherein materials of the source, the drain, and the first gate comprise silver, gold, copper, aluminum, nickel, platinum, molybdenum, indium tin oxide, indium zinc oxide, or a combination thereof, or the materials of the source, the drain, and the first gate comprise polyaniline (PANI), poly(3,4-ethylenedioxythiophene) (PEDOT), or graphene.

Assignees

• Wistron Corp

Inventors

• Peng Yu-Jung
• Hsieh Hsin-Yu
• Wang Yi-Kai

Classifications

• H01L51/0023

  Electricity · mapped topic

• H01L27/283

  Electricity · mapped topic

• H01L51/0541

  Electricity · mapped topic

• H01L51/0554

  Electricity · mapped topic

• H01L51/0018 Primary

  Electricity · mapped topic