Semiconductor device manufacturing method and semiconductor device

Patent metadata

Field	Value
Publication number	US-9954094-B2
Application number	US-201615008978-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Feb 16, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p − type drift layer comprised of the area in which the p type impurity is introduced, as well as an n − type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a p type semiconductor substrate;
a p type first semiconductor region formed over the semiconductor substrate;
an n type second semiconductor region formed adjacent to the first semiconductor region over the semiconductor substrate;
an n type third semiconductor region formed over the first semiconductor region and over the second semiconductor region;
a p type fourth semiconductor region formed over the third semiconductor region;
a first groove penetrating through a top surface of the first semiconductor region, after passing through the fourth semiconductor region and through the third semiconductor region;
a gate insulating film formed in an inner wall of the first groove;
a gate electrode formed over the first gate insulating film so as to fill the first groove;
a source electrode contacting the third semiconductor region and the fourth semiconductor region; and
a drain electrode electrically coupled to the semiconductor substrate;
wherein a transistor is formed by the first semiconductor region, the third semiconductor region, the fourth semiconductor region, the gate insulating film, and the gate electrode,
wherein the first semiconductor region and the second semiconductor region are formed by implanting ions of a p type first impurity into a first area of an n type semiconductor film that is epitaxially grown over the semiconductor substrate, and by not implanting ions of the first impurity into a second area of the semiconductor film, the second area being adjacent to the first area,
wherein the first semiconductor region is comprised of the first area in which the first impurity is introduced, and
wherein the second semiconductor region is comprised of the second area in which the first impurity is not introduced.

2. The semiconductor device according to claim 1 ,
wherein the first semiconductor region is brought into contact with the semiconductor substrate.

3. The semiconductor device according to claim 1 ,
wherein an n type second impurity is introduced into the semiconductor film,
wherein the second semiconductor region is comprised of the second area in which the second impurity is introduced and the first impurity is not introduced,
wherein an n type third impurity is introduced into the third semiconductor region, and
wherein the concentration of the third impurity in the third semiconductor region is higher than the concentration of the second impurity in the second semiconductor region.

4. The semiconductor device according to claim 1 ,
wherein an inverter is formed by the transistor.

Assignees

• Renesas Electronics Corp

Inventors

• Ohtani Kinya
• Nishimura Yasuhiro

Classifications

• H10P30/22

  using masks · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title