Group III-Nitride compound heterojunction tunnel field-effect transistors and methods for making the same

Patent metadata

Field	Value
Publication number	US-9954085-B2
Application number	US-201615194039-A
Country	US
Kind code	B2
Filing date	Jun 27, 2016
Priority date	Oct 28, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (In x Ga 1-x N) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.

First claim

We claim:

1. A tunnel field-effect transistor comprising:
a source-layer comprising p-type GaN;
a drain-layer comprising n-type GaN; a gate; and
an interlayer interfaced between the source-layer and the drain-layer, wherein the interlayer comprises an InN layer,
wherein the source layer, the drain-layer, and the interlayer are positioned linearly and the gate is positioned substantially around the source-layer, the drain-layer, and the interlayer, such that the source-layer, the drain-layer, and the interlayer are arranged in a cylindrical nanowire configuration; and
wherein a thickness of the interlayer is based on a width of the gate, wherein the thickness of the interlayer is based on a relationship between energy band and tunneling distance that an interlayer thickness of 1.7 nanometers for a gate width of 20 nanometers provides for maximum on-current density.

2. The tunnel field-effect transistor of claim 1 , wherein the thickness of the interlayer is within the range of about 0.1 to 3.0 nanometers.

3. A tunnel field-effect transistor comprising:
a source-layer comprising p-type GaN;
a drain-layer comprising n-type GaN; and
an interlayer interfaced between the source-layer and the drain-layer, wherein the interlayer comprises an InN layer and a graded InGaN layer,
wherein the source-layer, the drain-layer, and the interlayer are positioned linearly and a gate is positioned substantially around the source-layer, the drain-layer, and the interlayer, such that the source-layer, the drain-layer, and the interlayer are arranged in a cylindrical nanowire configuration; and
wherein a thickness of the interlayer is based on a width of the gate, wherein the thickness of the interlayer is based on a relationship between energy band and tunneling distance that an interlayer thickness of 1.7 nanometers for a gate width of 20 nanometers provides for maximum on-current density.

4. The tunnel field-effect transistor of claim 3 , wherein the graded InGaN layer is linearly graded about its thickness.

5. The tunnel field-effect transistor of claim 4 , wherein the graded InGaN layer is linearly graded about its thickness such that: x is linearly increased from 0 to 1 for In x Ga 1-x N.

6. The tunnel field-effect transistor of claim 3 , wherein the thickness of the graded InGaN layer is based on the thickness of the InN layer, wherein the thickness of the graded InGaN layer is based on an observed relationship that a graded InGaN layer thickness of 0.6 nanometers provides for maximum on-current density.

7. A tunnel field-effect transistor comprising:
a source-layer comprising p-type GaN;
a drain-layer comprising n-type GaN; and
an interlayer interfaced between the source-layer and the drain-layer, wherein the interlayer comprising an InGaN layer and a graded InGaN layer;
wherein the source-layer, the drain-layer, and the interlayer are positioned linearly and a gate is positioned substantially around the source-layer, the drain-layer, and the interlayer, such that the source-layer, the drain-layer, and the interlayer are arranged in a cylindrical nanowire configuration; and
wherein a thickness of the interlayer is based on a width of the gate, wherein the thickness of the interlayer is based on a relationship between energy band and tunneling distance that an interlayer thickness of 1.7 nanometers for a gate width of 20 nanometers provides for maximum on-current density.

8. The tunnel field-effect transistor of claim 7 , wherein a In mole faction of the InGaN layer cause the tunnel field-effect transistor to achieve a switching slope of less than 60 millivolts per decade.

Assignees

• Univ Notre Dame Du Lac
• Univ Of Notre Dame Due Lac

Inventors

• Fay Patrick
• Cao Lina
• Jena Debdeep
• Li Wenjun

Classifications

• H01L29/66522

  Electricity · mapped topic

• H01L29/66977 Primary

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/0669

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic