Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9953997-B2
Application number	US-201615249590-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Sep 2, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
stacks on a substrate, each of the stacks comprising a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes;
a vertical channel connected to the substrate; and
a separation pattern disposed between the stacks,
wherein each of the gate electrodes comprises:
a first metal pattern disposed between the insulating patterns to define a recess region recessed toward the vertical channel; and
a second metal pattern disposed in the recess region, and
wherein the first and second metal patterns contain the same metallic material and have mean grain sizes different from each other.

2. The semiconductor memory device of claim 1 , wherein a first mean grain size of the metallic material in the first metal patterns is greater than a second mean grain size of the metallic material in the second metal patterns.

3. The semiconductor memory device of claim 1 , wherein the second metal patterns have a first vertical thickness at a region that is adjacent the vertical channel and a second vertical thickness at another region that is adjacent the separation pattern, and
the first vertical thickness is substantially the same as the second vertical thickness.

4. The semiconductor memory device of claim 1 , wherein the second metal patterns have a first vertical thickness at a region that is adjacent the vertical channel and a second vertical thickness at another region that is adjacent the separation pattern, and
the second vertical thickness is greater than the first vertical thickness.

5. The semiconductor memory device of claim 4 , wherein the second vertical thickness of the second metal patterns is smaller than a vertical thickness of the gate electrodes.

6. The semiconductor memory device of claim 4 , wherein the second vertical thickness of the second metal patterns is substantially the same as a vertical thickness of the gate electrodes.

7. The semiconductor memory device of claim 1 , wherein the second metal patterns has a vertical thickness that decreases in a direction from the separation pattern toward the vertical channel.

8. The semiconductor memory device of claim 1 , further comprising an insulating layer which is disposed between the vertical channel and each of the first metal patterns and which covers top and bottom surfaces of the respective first metal patterns,
wherein the second metal patterns are between the separation pattern and the respective first metal patterns and are in contact with the insulating layer.

9. The semiconductor memory device of claim 1 , wherein a portion of the second metal patterns that is adjacent the separation pattern has a vertical length that decreases in a direction from the separation pattern toward the vertical channel, and
another portion of the second metal patterns that is adjacent the vertical channel has a substantially uniform vertical length.

10. The semiconductor memory device of claim 1 , wherein each of the first and second metal patterns contains tungsten.

11. A semiconductor memory device, comprising:
stacks on a substrate, each of the stacks comprising a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes;
a vertical channel connected to the substrate; and
a separation pattern disposed between the stacks,
wherein each of the gate electrodes comprises:
a first metal pattern disposed between the insulating patterns to define a recess region recessed toward the vertical channel; and
a second metal pattern disposed in the recess region, the second metal pattern having a first vertical thickness at a region that is adjacent the vertical channel and a second vertical thickness at another region that is adjacent the separation pattern,
wherein the second vertical thickness is greater than the first vertical thickness.

12. The semiconductor memory device of claim 11 , wherein the second metal pattern has a vertical thickness that decreases in a direction from the separation pattern toward the vertical channel.

13. The semiconductor memory device of claim 11 , wherein the second vertical thickness of the second metal patterns is substantially the same as a vertical thickness of the gate electrodes.

14. The semiconductor memory device of claim 11 , wherein the second vertical thickness of the second metal patterns is smaller than a vertical thickness of the gate electrodes.

15. The semiconductor memory device of claim 11 , wherein the first and second metal patterns contain the same metal material, and
the first metal patterns have a first mean grain size that is larger than a second mean grain size of the second metal patterns.

16. A semiconductor memory device, comprising:
a plurality of gate electrodes that are vertically stacked on a substrate, each gate electrode including a first metal pattern and a second metal pattern that fills a recess region defined by the first metal pattern,
wherein the first and second metal patterns comprise the same material but have different mean grain sizes.

17. The semiconductor memory device of claim 16 , further comprising an insulating layer, a separation pattern and a vertical channel, wherein the gate electrodes are disposed between the separation pattern and the vertical channel, the insulating layer is between each gate electrode and the vertical channel, and the insulating layer further covers top and bottom surfaces of each of the gate electrodes.

18. The semiconductor memory device of claim 17 , wherein portions of the second metal patterns that are adjacent the vertical channel have a first vertical thickness and portions of the second metal patterns that are adjacent the separation pattern have a second vertical thickness, the second vertical thickness being greater than the first vertical thickness.

19. The semiconductor memory device of claim 16 , wherein each first metal pattern is generally U-shaped and each second metal pattern fills an interior of the respective one of the generally U-shaped first metal patterns.

20. The semiconductor memory device of claim 17 , wherein the separation pattern directly contacts each first metal pattern and each second metal pattern.

Assignees

• Park Joyoung
• Han Hauk
• Lee Seok Won
• Lee Jeonggil
• Park Jinwoo
• Yoon Kihyun
• Lim Hyunseok
• Ha Jooyeon
• Samsung Electronics Co Ltd

Inventors

• Park Joyoung
• Han Hauk
• Lee Seok-Won
• Lee Jeonggil
• Park Jinwoo
• Yoon Kihyun
• Lim Hyunseok
• Ha Jooyeon

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/045

  for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title