Implementing hidden security key in eFuses

Patent metadata

Field	Value
Publication number	US-9953720-B2
Application number	US-201514696251-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	Dec 17, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. The circuit includes a race condition circuit coupled to a latching structure. The race condition circuit is characterized including respective driver strengths of each stage in the race as well as a sampling clock during chip testing. The data is used to store drive strengths for each stage in eFuses and is used to get a logical one or logical zero out of the final latching stage of the race condition circuit.

First claim

What is claimed is:

1. A method for implementing a hidden security key in a chip, said method comprising:
providing a data bit generator including a plurality of delay blocks coupled to a latching structure; said data bit generator receiving respective bit inputs for each delay block and a sampling clock and providing a data bit output;
providing a race condition circuit; characterizing said race condition circuit during chip testing, said race condition circuit including a plurality of said data bit generators receiving a start race input and respective multiple deriver strength bits and yielding a plurality of output data buts defining the hidden security key; storing said respective multiple driver strength bits in the chip for each of said plurality of said data bit generators in said race condition circuit, and
generating the hidden security key with the plurality of output data bits.

2. The method as recited in claim 1 wherein each of said plurality of delay blocks receive an input and provide a programmable delay output.

3. The method as recited in claim 2 wherein providing a data bit generator including a plurality of delay blocks includes providing each of said plurality of delay blocks with a plurality of P-channel field effect transistors (PFETs) and a plurality of N-channel field effect transistors (NFETs), a respective PFET, NFET receiving a respective strength bit gate input.

4. The method as recited in claim 2 wherein providing a data bit generator including a plurality of delay blocks includes providing said each of said plurality of delay blocks includes a plurality of plurality of delay branches, each delay branch includes a stack of three transistor inverters, each inverter having a respective capacitor and coupled to a 2-input NAND gate, each inverter providing a first NAND gate input, and a decode providing a second NAND gate input, said receiving a respective delay bits input and a 4-input NAND gate receiving an input from each said 2-input NAND gate and providing a unique and characterizable delay output.

5. The method as recited in claim 1 wherein said respective multiple driver strength bits are used to store drive strengths for each stage.

Assignees

• IBM

Inventors

• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G11C29/54

  Arrangements for designing test circuits, e.g. design for test [DFT] tools · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G06F21/73

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title