Memory device

Patent metadata

Field	Value
Publication number	US-9953707-B2
Application number	US-201615257313-A
Country	US
Kind code	B2
Filing date	Sep 6, 2016
Priority date	Mar 7, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

According to one embodiment, a memory device includes a sense amplifier including a first input node and a second input node, a first path including a memory cell to be selectively connected to the first input node, and a second path including a reference cell to be selectively connected to the second input node, and is configured to change an input value at the second input node in accordance with the state of the memory cell.

First claim

What is claimed is:

1. A memory device comprising:
a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node;
a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and
a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node,
wherein the input value at the second input node of the sense amplifier is changed such that a change amount of an input value between two different temperatures T 2 and (T 2 +ΔT) in a second temperature region, at a temperature higher than in a first temperature region, of the memory cell becomes larger than a change amount of an input value between two different temperatures T 1 and (T 1 +ΔT) in the first temperature region of the memory cell,
where ΔT is an increase amount of the temperature.

2. The memory device according to claim 1 , wherein the change amount of the input value at the second input node is proportional to a leak current in the first path and has a proportionality constant smaller than 1.

3. The memory device according to claim 1 , wherein a reference current generation circuit provided with a replica circuit is connected to the second input node of the sense amplifier.

4. The memory device according to claim 3 , wherein the replica circuit comprises a leak monitor circuit configured to monitor a leak current in the first path.

5. The memory device according to claim 4 , wherein the leak monitor circuit comprises a replica of the memory cell.

6. The memory device according to claim 4 , wherein the leak monitor circuit comprises a replica of a local column switch configured to select or unselect the memory cell.

7. The memory device according to claim 1 , wherein a current generation circuit provided with a replica circuit is connected to the first input node of the sense amplifier.

8. The memory device according to claim 1 , wherein the memory cell comprises a resistance change memory element as a memory element.

9. The memory device according to claim 1 , wherein the memory cell comprises a magnetoresistive element as a memory element.

Assignees

• Toshiba Memory Corp

Inventors

• Katayama Akira

Classifications

• G11C11/1659

  Cell access · CPC title

• G11C11/1653

  Address circuits or decoders · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title