Design/technology co-optimization platform for high-mobility channels CMOS technology

Patent metadata

Field	Value
Publication number	US-9953125-B2
Application number	US-201615183333-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Jun 15, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Embodiments of the present invention may provide the capability to design SRAM cells may be designed that is compatible with the requirements of InGaAs integration by selective epitaxy in SiO 2 cavities without sacrificing density and area scaling. In an embodiment of the present invention, a computer-implemented method for designing a hybrid integrated circuit may comprise receiving data representing a layout of a static random-access memory cell array, identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array, selecting from among the identified areas at least one area, expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area, and marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region.

First claim

What is claimed is:

1. A computer-implemented method for CMOS manufacturing a hybrid integrated circuit comprising:
receiving, at a hardware processor, data representing a layout of a static random-access memory cell array;
identifying, by the hardware processor, areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array;
selecting, by the hardware processor, from among the identified areas at least one area;
expanding, by the hardware processor, the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area; and
marking, by the hardware processor, as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region, and
growing a III-V layer of semiconductor material at a marked seed location by selective epitaxy.

2. The method of claim 1 , wherein each selected area is expanded length-wise, width-wise, or both, to a maximum area or by a pre-determined amount.

3. The method of claim 1 , wherein the hybrid integrated circuit comprises Si or SiGe static random-access memory circuits and the III-V semiconductor material.

4. The method of claim 3 , wherein the III-V semiconductor material is InGaAs.

5. The method of claim 4 , further comprising:
determining, by the hardware processor, whether a spacing between active areas in the layout of the static random-access memory cell array is greater than a diameter of a Si seed.

6. The method of claim 4 , wherein the static random-access memory cell array comprises fin field effect transistors, and the method further comprises:
determining, by the hardware processor, whether a spacing between fins of adjacent transistors is greater than a fin pitch of the fin field effect transistors.

7. A computer program product for CMOS manufacturing a hybrid integrated circuit, the computer program product comprising a non-transitory computer readable storage having program instructions embodied therewith, the program instructions executable by a computer, to cause the computer to perform a method comprising:
identifying areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array;
selecting from among the identified areas at least one area;
expanding the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area; and
marking as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region, and
growing a III-V layer of semiconductor material at a marked seed location by selective epitaxy.

8. The computer program product of claim 7 , wherein each selected area is expanded length-wise, width-wise, or both, to a maximum area or by a pre-determined amount.

9. The computer program product of claim 7 , wherein the hybrid integrated circuit comprises Si or SiGe static random-access memory circuits and the III-V semiconductor material.

10. The computer program product of claim 9 , wherein the III-V semiconductor material is InGaAs.

11. The computer program product of claim 10 , wherein the program instructions further causes the computer to perform:
determining whether a spacing between active areas in the layout of the static random-access memory cell array is greater than a diameter of a Si seed.

12. The computer program product of claim 10 , wherein the static random-access memory cell array comprises fin field effect transistors, and the program instructions further causes the computer to perform:
determining whether a spacing between fins of adjacent transistors is greater than a fin pitch of the fin field effect transistors.

13. A system for CMOS manufacturing a hybrid integrated circuit, the system comprising:
a processor,
a memory accessible by the processor, and computer program instructions stored in the memory and executable by the processor to perform a method to:
receive data representing a layout of a static random-access memory cells of a static random-access memory cell array;
identify areas between active channel regions that do not overlap with transistor gates of static random-access memory cells of the static random-access memory cell array;
selecting from among the identified areas at least one area;
expand the selected areas to determine whether the expanded area intersects with a p-doped active Si semiconductor or p-channel semiconductor area; and
mark as Si seed locations the identified expanded areas that do not intersect on both sides with a channel active transistor region, and
grow a III-V layer of semiconductor material at a marked seed location by selective epitaxy.

14. The system of claim 13 , wherein to expand the selected areas, said processor is further configured to: expand each selected area length-wise, width-wise, or both, to a maximum area or by a pre-determined amount.

15. The system of claim 13 , wherein the hybrid integrated circuit comprises Si or SiGe static random-access memory circuits and the III-V semiconductor material.

16. The method of claim 15 , wherein the III-V semiconductor material is InGaAs.

17. The system of claim 16 , wherein said processor is further configured to:
determine whether a spacing between active areas in the layout of the static random-access memory cell array is greater than a diameter of a Si seed.

18. The system of claim 16 , wherein the static random-access memory cell array comprises fin field effect transistors, and the processor is further configured to:
determine whether a spacing between fins of adjacent transistors is greater than a fin pitch of the fin field effect transistors.

Assignees

• IBM

Inventors

• Caimi Daniele
• Czornomaz Lukas
• Deshpande Veeresh V
• Djara Vladimir
• Fompeyrine Jean

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/36 Primary

  Circuit design at the analogue level · CPC title

• H01L27/0886

  Electricity · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic

• H01L27/1104

  Electricity · mapped topic