Methods and systems for direct memory access operations

Patent metadata

Field	Value
Publication number	US-9952979-B1
Application number	US-201514597030-A
Country	US
Kind code	B1
Filing date	Jan 14, 2015
Priority date	Jan 14, 2015
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Systems and methods for a direct memory access (DMA) operation are provided. The method includes receiving a host memory address by a device coupled to a computing device; storing the host memory address at a device memory by a DMA engine; receiving a packet at the device for the computing device; instructing the DMA engine by a device processor to retrieve the host memory address from the device memory; retrieving the host memory address by the DMA engine without the device processor reading the host memory address; and transferring the packet to the computing device by a DMA operation.

First claim

What is claimed is:

1. A machine implemented method, comprising:
posting a host memory address at a computing device memory by a device driver executed by the computing device that interfaces with a device configured to receive data from a network; wherein the host memory address provides a location of the computing device memory for the device for placing received network data;
notifying the device coupled to the computing device by the device driver that the host memory address is posted at the computing device memory;
instructing a direct memory access (DMA) engine of the device by a device processor to retrieve the host memory address from the computing device memory;
retrieving the host memory address from the computing device memory by the DMA engine and storing the host memory address at a device memory located at the device by the DMA engine;
receiving a packet at the device for the computing device;
in response to receiving the packet, instructing the DMA engine by the device processor to retrieve the host memory address from the device memory for placing the packet to the location of the computing device memory;
retrieving the host memory address from the device memory by the DMA engine without the device processor having to read the host memory address from the device memory; and
transferring the packet by the DMA engine using a DMA operation to the location of the computing device memory identified by the host memory address read by the DMA engine from the device memory.

2. The method of claim 1 , wherein the device is coupled to the computing device using a peripheral bus.

3. The method of claim 1 , wherein the device is a host bus adapter.

4. The method of claim 1 , wherein the device is a converged network adapter.

5. The method of claim 1 , wherein the device is a network interface card.

6. The method of claim 1 , wherein the device is coupled to the computing device via a PCI-Express link.

7. A non-transitory, machine readable storage medium having stored thereon instructions for performing a method, comprising machine executable code which when executed by at least one machine, causes the machine to:
post a host memory address at a computing device memory by a device driver executed by the computing device that interfaces with a device configured to receive data from a network; wherein the host memory address provides a location of the computing device memory for the device for placing received network data;
notify the device coupled to the computing device by the device driver that the host memory address is posted at the computing device memory;
instruct a direct memory access (DMA) engine of the device by a device processor to retrieve the host memory address from the computing device memory;
retrieve the host memory address from the computing device memory by the DMA engine and storing the host memory address at a device memory located at the device by the DMA engine;
receive a packet at the device for the computing device;
in response to the received packet, instruct the DMA engine by the device processor to retrieve the host memory address from the device memory for placing the packet to the location of the computing device memory;
retrieve the host memory address from the device memory by the DMA engine without the device processor having to read the host memory address from the device memory; and
transferring the packet by the DMA engine using a DMA operation to the location of the computing device memory identified by the host memory address read by the DMA engine from the device memory.

8. The non-transitory, storage medium of claim 7 , wherein the device is coupled to the computing device using a peripheral bus.

9. The non-transitory, storage medium of claim 7 , wherein the device is a host bus adapter.

10. The non-transitory, storage medium of claim 7 , wherein the device is a converged network adapter.

11. The non-transitory, storage medium of claim 7 , wherein the device is a network interface card.

12. The non-transitory, storage medium of claim 7 , wherein the device is coupled to the computing device via a PCI-Express link.

13. A system, comprising:
a computing device coupled to a device having a device processor and a direct memory access (DMA) engine; wherein the device is configured to receive data from a network;
wherein a device driver executed by the computing device posts a host memory address at a computing device memory and notifies the device that the host memory address is posted at the computing device memory, where the host memory address provides a location for placing by the device received network data at the computing device memory; wherein the device processor instructs the DMA engine to retrieve the host memory address from the computing device memory and the DMA engine retrieves the host memory address from the computing device memory without the device processor accessing the host memory address and stores the host memory address at a device memory located at the device; and
wherein when the device receives a packet for the computing device, the device processor instructs the DMA engine to retrieve the host memory address from the device memory; the DMA engine retrieves the host memory address without the device processor having to read the host memory address; and then transfers the packet by a DMA operation to the location of the computing device memory identified by the host memory address read by the DMA engine from the device memory.

14. The system of claim 13 , wherein the device is coupled to the computing device using a peripheral bus.

15. The system of claim 13 , wherein the device is a host bus adapter or a converged network adapter.

16. The system of claim 13 , wherein the device is a network interface card.

17. The system of claim 13 , wherein the device is coupled to the computing device via a PCI-Express link.

Assignees

• Qlogic Corp
• Cavium Inc

Inventors

• Mukherjee Abhishek

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F2212/303

  In peripheral interface, e.g. I/O adapter or channel · CPC title

• G06F2213/2806

  Space or buffer allocation for DMA transfers · CPC title