Fault detection apparatus and method

Patent metadata

Field	Value
Publication number	US-9952922-B2
Application number	US-201314899595-A
Country	US
Kind code	B2
Filing date	Jul 18, 2013
Priority date	Jul 18, 2013
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Apparatus suitable for detecting a fault in a processor comprises a monitor which receives input and output signals from the processor and generates a hash index key which is used to access entries in a hash table. The entries may include actions such as setting a timer so that the response of an output to a change of state of an input may be confirmed as valid within a specified time interval.

First claim

The invention claimed is:

1. A method for detecting a fault in a device, the method comprising;
receiving from the device, a first signal to be monitored, said first signal to be monitored having a value;
generating a first hash index key for the first signal to be monitored;
searching, using said generated first hash index key, a hash table for an entry matching the value of the received first signal;
if a matching entry is not found, completing a first action; and
if a matching entry is found, completing a second action associated with the found matching entry, wherein the second action comprises:
enabling a first timer and a second timer, wherein a time interval of the second timer is longer than a time interval of the first timer;
receiving a second signal to be monitored;
said second signal having a value;
generating a second hash index key for said second signal;
searching, using the generated second hash index key, the hash table for an entry matching the value of the received second signal,
generating a fault notification signal in response to an entry matching the value of the received second signal being found before the first timer expires; and
generating the fault notification signal in response to the second timer expiring before an entry matching the value of the received second signal is found.

2. The method of claim 1 , wherein said first action comprises generating the fault notification signal.

3. The method of claim 1 wherein said first action comprises putting the device into a failsafe mode of operation.

4. The method of claim 1 wherein the timer sets one or more predetermined time intervals and if no matching entry is found within a time interval set by the timer, completing a third action.

5. The method of claim 4 wherein the third action comprises generating a fault notification signal.

6. The method of claim 4 wherein the third action comprises putting the device into a failsafe mode of operation.

7. The method of claim 4 wherein the third action comprises generating an interrupt.

8. Fault detection apparatus to detect a fault in a device, said apparatus comprising:
a memory to store a hash table, and
a monitor circuit arranged to receive from the device, a signal to be monitored, said signal to be monitored having a value, to generate a first hash index key for the signal to be monitored, to search, via said generated first hash index key, the hash table for an entry matching the value of the received signal, and if a matching entry is not found, to complete a first action and if a matching entry is found, to complete a second action associated with the found matching entry, wherein the second action comprises: the monitor circuit to enable a first timer and a second timer, wherein a time interval of the second timer is longer than a time interval of the first timer, to receive a second signal to be monitored, said second signal having a value, to generate a second hash index key for said second signal, to search, using the generated second hash index key, the hash table for an entry matching the value of the received second signal, to generate a fault notification signal in response to an entry matching the value of the received second signal being found before the first timer expiring before, and to generate the fault notification signal in response to the second timer expiring before an entry matching the value of the received second signal is found.

9. The fault detection apparatus of claim 8 comprising the first and second timer arranged to set one or more predetermined time intervals during which the hash table is searched for a matching entry.

10. The fault detection apparatus of claim 8 wherein the fault detection apparatus is implemented in one or more integrated circuit devices.

11. A non-transitory tangible computer program product having executable program code stored thereon for execution by a processor to perform a method in accordance with claim 1 .

12. The tangible computer program product of claim 11 wherein the tangible computer program product comprises at least one from a group consisting of: a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a Read Only Memory, a Programmable Read Only Memory, an Erasable Programmable Read Only Memory, EPROM, an Electrically Erasable Programmable Read Only Memory and a Flash Memory.

Assignees

• Edmiston Graham
• Devine Alan
• Mcmenamin David
• Roberston Andrew
• Scobie James Andrew Collier
• Nxp Usa Inc

Inventors

• Edmiston Graham
• Devine Alan
• Mcmenamin David
• Roberston Andrew
• Scobie James Andrew Collier

Classifications

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/28

  by checking the correct order of processing (G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19) · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title