Method and system to provide user-level multithreading

Patent metadata

Field	Value
Publication number	US-9952859-B2
Application number	US-201615088043-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2004
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

First claim

What is claimed is:

1. A processor for executing multiple user-level threads comprising:
a shared application state storage pool including one or more control registers allocated to be shared by a first user-level thread and a second user-level thread, and one or more shared architectural registers allocated to be visible to the first user-level thread and to the second user-level thread through one or more user-level instructions, wherein the one or more shared architectural registers are allocated to provide communication between the first user-level thread and the second user-level thread;
a private application state storage pool including: a first instruction pointer for the first user-level thread, a first one or more private architectural registers allocated to be visible to only the first user-level thread, a second instruction pointer for the second user-level thread and a second one or more private architectural registers allocated to be visible to only the second user-level thread; and
thread logic to create the second user-level thread in response to a fork instruction encountered during execution of the first user-level thread, wherein the fork instruction is part of an Instruction Set Architecture available to the first user-level thread at a user privilege level.

2. The processor of claim 1 wherein the one or more shared architectural registers are configurably allocated using a programmable bit-vector to be selected as said one or more shared architectural registers.

3. The processor of claim 2 wherein the one or more shared architectural registers are configured to be atomically updated to synchronize data between the first user-level thread and the second user-level thread.

4. The processor of claim 3 further comprising a hardware re-namer to allocate registers from either the shared application state storage pool or from the private application state storage pool as specified by said programmable bit-vector.

5. The processor of claim 1 wherein said one or more control registers includes a field, when set, to enable multithreading architecture extensions for user-level multithreading.

6. A processor for executing multiple user-level threads comprising:
a shared application state storage pool including one or more control registers allocated to be shared by a first user-level thread and a second user-level thread, and one or more shared architectural registers allocated to be visible to the first user-level thread and to the second user-level thread through one or more a user-level instructions, wherein the one or more architectural registers are configurably allocated using a programmable bit-vector to be selected as said one or more shared architectural registers to provide communication between the first user-level thread and the second user-level thread;
a private application state storage pool including: a first instruction pointer for the first user-level thread, a first one or more private architectural registers allocated to be visible to only the first user-level thread, a second instruction pointer for the second user-level thread and a second one or more private architectural registers allocated to be visible to only the second user-level thread; and
a hardware re-namer to allocate registers from either the shared application state storage pool or from the private application state storage pool as specified by said programmable bit-vector.

7. The processor of claim 6 wherein said one or more shared architectural registers are configured to be atomically updated to synchronize data between the first user-level thread and the second user-level thread.

8. The processor of claim 6 further comprising thread logic to create the second user-level thread in response to a fork instruction encountered during execution of the first user-level thread, wherein the fork instruction is part of an Instruction Set Architecture available to the first user-level thread at a user privilege level.

9. The processor of claim 6 wherein said one or more control registers includes a field, when set, to enable multithreading architecture extensions for user-level multithreading.

10. The processor of claim 9 wherein one of said one or more control registers that includes the field to enable multithreading architecture extensions for user-level multithreading is a model specific register.

11. The processor of claim 6 wherein one of said one or more control registers allocated to be shared by the first user-level thread and the second user-level thread contains one or more empty/full bit, corresponding to the one or more shared architectural registers, to be atomically updated to synchronize data between the first user-level thread and the second user-level thread.

12. A processor system for executing multiple user-level threads comprising:
a processing unit including,
a shared application state storage pool including one or more control registers allocated to be shared by a first user-level thread and a second user-level thread, and one or more shared architectural registers allocated to be visible to the first user-level thread and to the second user-level thread through one or more user-level instructions, wherein the one or more shared architectural registers are allocated to provide communication between the first user-level thread and the second user-level thread;
a private application state storage pool including: a first instruction pointer for the first user-level thread, a first one or more private architectural registers allocated to be visible to only the first user-level thread, a second instruction pointer for the second user-level thread and a second one or more private architectural registers allocated to be visible to only the second user-level thread; and
a hardware re-namer to allocate registers from either the shared application state storage pool or from the private application state storage pool; and

a dynamic random access memory coupled to the processor to hold operating system code.

13. The processor system of claim 12 wherein the one or more shared architectural registers are configurably allocated by said hardware re-namer using a programmable bit-vector from either the shared application state storage pool or from the private application state storage pool as specified by said programmable bit-vector.

14. The processor system of claim 13 wherein one of said one or more control registers allocated to be shared by the first user-level thread and the second user-level thread contains one or more empty/full bit, corresponding to the one or more shared architectural registers, to be atomically updated to synchronize data between the first user-level thread and the second user-level thread.

15. The processor system of claim 13 , said processing unit further comprising thread logic to create the second user-level thread in response to a fork instruction encountered during execution of the first user-level thread, wherein the fork instruction is part of an Instruction Set Architecture available to the first user-level thread at a user privilege level.

Assignees

• Intel Corp

Inventors

• Grochowski Ed
• Wang Hong
• Shen John P
• Wang Perry H
• Collins Jamison D
• Held James
• Kundu Partha
• Leviathan Raya
• Ngai Tin-Fook

Classifications

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/30003 Primary

  Arrangements for executing specific machine instructions · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/30101

  Special purpose registers · CPC title