Display device with positive polarity and negative polarity pixels and method for driving the same

Patent metadata

Field	Value
Publication number	US-9952478-B2
Application number	US-201414455442-A
Country	US
Kind code	B2
Filing date	Aug 8, 2014
Priority date	May 8, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Disclosed are a display device and a method of driving the same. The display device includes: a panel on which pixels, defined by intersections of a plurality of gate lines and a plurality of data lines, are alternately connected to one side and another side of the data line and the gate line; a data driver which supplies a data voltage having a different polarity to the data lines in odd columns even columns; and, a gate driver which supplies a gate voltage, which has first polarity and corresponds to a data voltage having the first polarity, to gate lines in odd rows, and supplies a gate voltage, which has a second polarity, and corresponds to a data voltage having the second polarity, to gate lines in even rows.

First claim

What is claimed is:

1. A display device comprising:
a first gate line;
a second gate line;
a third gate line;
a first row of pixels between the first gate line and the second gate line;
a second row of pixels between the second gate line and the third gate line, wherein all of the pixels in the first row of pixels and the second row of pixels belong to either a first subset or a second subset, the first subset of the pixels supplied with first data voltages of a first polarity during a frame and the second subset of the pixels supplied with second data voltages of a second polarity opposite from the first polarity during the frame, wherein each pixel in the first subset of the pixels in the first row is connected to the first gate line, each pixel in the first subset of the pixels in the second row is connected to the third gate line and each pixel in the second subset of the pixels is connected to the second gate line;
first data lines connected to the first subset of pixels and that provide the first data voltages of the first polarity and do not provide the second data voltages of the second polarity during the frame, wherein a data line of the first data lines is connected to a pixel of the first subset of the pixels in the first row and a pixel of the first subset of the pixels in the second row; and
second data lines connected to the second subset of the pixels and that provide the second data voltages of the second polarity and do not provide the first data voltages of the first polarity during the frame, wherein a data line of the second data lines is connected to a pixel of the second subset of the pixels in the first row and a pixel of the second subset of the pixels in the second row,
wherein a maximum gate voltage and a minimum gate voltage of a first gate signal for the first gate line are set in accordance with a range of the first data voltages, and a maximum gate voltage and a minimum gate voltage of a second gate signal for the second gate line are set in accordance with a range of the second data voltages,
wherein the maximum gate voltage of the first gate signal has a different level than the maximum gate voltage of the second gate signal, and the minimum gate voltage of the first gate signal has a different level than the minimum gate voltage of the second gate signal.

2. The display device of claim 1 , further comprising:
a data driver to supply the first data voltages of the first polarity to the first data lines and to supply the second data voltages of the second polarity to the second data lines.

3. The display device of claim 2 , further comprising:
a multiplexing circuit to selectively route the first and second data voltages from the data driver to the first data lines or the second data lines.

4. The display device of claim 2 , wherein the first data lines are odd data lines and the second data lines are even data lines.

5. The display device of claim 1 , further comprising:
a power supply to generate four supply voltages having different magnitudes, the four supply voltages including a first supply voltage, a second supply voltage, a third supply voltage and a fourth supply voltage; and
a level shifter to generate the first gate signal based on the first supply voltage and the second supply voltage, and to generate the second gate signal based on the third supply voltage and the fourth supply voltage.

6. The display device of claim 5 , wherein the first supply voltage is higher than the third supply voltage, and the second supply voltage is higher than the fourth supply voltage.

7. The display device of claim 1 , wherein the first subset of the pixels alternate with the second subset of the pixels in the row of pixels.

8. The display device of claim 1 , wherein the first gate line is an odd gate line and the second gate line is an even gate line.

9. The display device of claim 1 , wherein
each pixel in the first subset of pixels includes a respective first transistor, a gate of the respective first transistor connected to the first gate line, and
each pixel in the second subset of pixels includes a respective second transistor, a gate of the respective second transistor connected to the second gate line.

10. The display device of claim 9 ,
wherein the first data voltages are generated to be in a first voltage range from a reference voltage to a positive maximum voltage, and a high voltage level of the first gate signal supplied to the first gate line is substantially equal to a first gate-source turn on voltage of the respective first transistor plus the positive maximum voltage of the first voltage range, and
wherein the second data voltages are generated to be in a second voltage range from a negative minimum voltage to the reference voltage, and a high voltage level of the second gate signal supplied to the second gate line is substantially equal to a second gate-source turn on voltage of the respective second transistor plus the reference voltage.

11. The display device of claim 1 , wherein the first polarity and the second polarity switch polarity with each frame.

12. The display device of claim 1 , wherein the first polarity is a positive polarity and the second polarity is a negative polarity.

13. A method of operation in a display device having a first row of pixels between a first gate line and a second gate line and a second row of pixels between the second gate line and a third gate line, wherein all of the pixels in the first row of pixels and the second row of pixels belong to either a first subset or a second subset, wherein each pixel in the first subset of pixels in the first row is connected to the first gate line, each pixel in the first subset of pixels in the second row is connected to the third gate line, and each pixel in the second subset of pixels is connected to the second gate line, the method comprising:
supplying the first subset of the pixels with first data voltages of a first polarity via first data lines during a frame, a pixel of the first subset of pixels in the first row and a pixel of the first subset of pixels in the second row being supplied with a data voltage of the first data voltages via a data line of the first data lines;
supplying the second subset of the pixels with second data voltages of a second polarity opposite from the first polarity via second data lines during the frame, the second data voltages of the second polarity not supplied via the first data lines during the frame, and the first data voltages of the first polarity not supplied via the second data lines during the frame;
supplying a first gate signal to each pixel in the first subset of the pixels in the first row via the first gate line; and
supplying a second gate signal to each pixel in the second subset of the pixels via the second gate line,
wherein a maximum gate voltage and a minimum gate voltage of the first gate signal are set in accordance with a range of the first data voltages, and a maximum gate voltage and a minimum gate voltage of the second gate signal are set in accordance with a range of the second data voltages,
wherein the maximum gate voltage of the first gate signal has a different level than the maximum gate voltage of the second gate signal, and the minimum gate voltage of the first gate signal has a different level than the minimum gate voltage of the second gate signal.

14. The method of claim 13 , further comprising:
generating the first gate signal based on a first high supply voltage and a first low supply voltage; and
generating the second gate signal based on a second high supply voltage and a second low supply voltage.

1

Assignees

• Lg Display Co Ltd

Inventors

• Hong Kwangpyo
• Song Joonglok

Classifications

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title