Transmit (tx) receive (rx) phased array system
US-2024322795-A1 · Sep 26, 2024 · US
US9952256B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9952256-B2 |
| Application number | US-201514635579-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 2, 2015 |
| Priority date | Dec 2, 2014 |
| Publication date | Apr 24, 2018 |
| Grant date | Apr 24, 2018 |
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The invention relates to a matching circuit for matching impedance values comprising an impedance element with an impedance value, which corresponds to a required total impedance value of the matching circuit, a structurally determined parasitic unit with a parasitic impedance value and a compensation unit with at least one first compensation element. The first compensation element provides a compensation impedance value which is the dual impedance value of the parasitic impedance value. Furthermore, a system comprising a first circuit unit and a second circuit unit with a matching circuit serving for the matching is provided. Also, a method for the compensation of parasitic units for matching purposes is provided.
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What is claimed is: 1. A matching circuit for matching an impedance value comprising: an impedance element with an impedance value, which corresponds to a required total impedance value of the matching circuit; a structurally determined parasitic unit with a parasitic impedance value; and a compensation unit with at least one first compensation element, wherein the first compensation element provides a compensation impedance value, which is the dual impedance value of the parasitic impedance value, wherein the compensation unit provides a second compensation element, and wherein the second compensation element provides an impedance value which corresponds to the required total impedance value. 2. The matching circuit according to claim 1 , wherein the impedance element is arranged in series configuration with the parasitic unit, and wherein the compensation unit is arranged in parallel configuration to this series configuration. 3. The matching circuit according to claim 2 , wherein the compensation unit is a series configuration comprising the first compensation element and the second compensation element. 4. The matching circuit according to claim 1 , wherein the impedance element is arranged in parallel configuration with the parasitic unit, and wherein the compensation unit is arranged in series configuration to this parallel configuration. 5. The matching circuit according to claim 4 , wherein the compensation unit is a parallel configuration comprising the first compensation element and the second compensation element. 6. The matching circuit according to claim 1 , wherein the dual impedance value of the first compensation element is referenced to the required total impedance value. 7. The matching circuit according to claim 1 , wherein the dual impedance value of the first compensation element is equal to the quotient of the square of the impedance value and the parasitic impedance value. 8. The matching circuit according to claim 1 , wherein the impedance element is an ohmic resistance element, especially with an impedance value of 50 ohms. 9. The matching circuit according to claim 1 , wherein, in each case, the parasitic unit and the first compensation element is a line with identical propagation constant and identical length. 10. The matching circuit according to claim 1 , wherein the parasitic unit is formed from a capacitance element, an inductance element and/or an ohmic resistance. 11. A system comprising a first circuit unit and a second circuit unit, wherein a matching circuit according to the claim 1 is present for the electrical matching of the first circuit unit to the second circuit unit. 12. The system according to claim 11 , wherein the second circuit unit and the matching circuit is an integral component of a measuring device, especially of a digital storage oscilloscope. 13. A method for compensating parasitic units for matching purposes with the method steps: checking the presence of a parasitic unit in series configuration or in parallel configuration to an impedance element, wherein the impedance element provides a required total impedance value; introduction of a compensation unit corresponding to the result of the checking step, wherein: in the presence of a parasitic unit in series configuration to the impedance element, the compensation unit is placed in parallel configuration to the series configuration; or in the presence of a parasitic unit in parallel configuration to the impedance element, the compensation unit is placed in series configuration to the parallel configuration; repetition of the checking step; and repetition of the placing step in the case of a presence of a further parasitic unit. 14. The method according to claim 13 , wherein the parasitic unit provides a parasitic impedance value; wherein the compensation unit provides at least one first compensation element; and wherein the first compensation element provides a compensation impedance value, which, in the case of a series-connected parasitic unit, is a series configuration of an impedance value and of the dual impedance value of the parasitic impedance value, or which, in the case of a parallel-connected parasitic unit, is a parallel configuration of an impedance value and of the dual impedance value of the parasitic impedance value.
Impedance-matching networks · CPC title
particularly adapted for storage oscilloscopes · CPC title
comprising distributed impedance elements together with lumped impedance elements · CPC title
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