Printed circuit board design for high speed application

Patent metadata

Field	Value
Publication number	US-9949360-B2
Application number	US-201213408062-A
Country	US
Kind code	B2
Filing date	Feb 29, 2012
Priority date	Mar 10, 2011
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. And, a second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.

First claim

What is claimed is:

1. A printed circuit board, comprising: a substrate having a top surface and a bottom surface;
a first conductive layer disposed on the top surface of the substrate, wherein the first conductive layer is in contact with the substrate and comprises three first signal nets, and two second signal nets, one on the left of the first signal nets and the other on the right of the first signal nets;
an outermost insulating layer disposed on the top surface of the substrate to cover the substrate and the first conductive layer, wherein the outmost insulating layer is in contact with the substrate and comprises openings to fully expose a top and sides of both the second signal nets; and
a second conductive layer disposed on the outermost insulating layer and substantially covering at least a portion of the first signal nets, including the exposed tops and sides of both the second signal nets,
wherein the second conductive layer which is able to provide one of a ground potential and a power potential is electrically connected to both the second signal nets through the openings,
wherein the first signal nets are disposed between the second signal nets, and the second signal nets comprises a via hole which is exposed from the openings,
wherein the entirety of the first conductive layer is disposed on the top surface of the substrate, and some of the top surface of the substrate is not covered by the first conductive layer.

2. The printed circuit board of claim 1 , further comprising a third conductive layer disposed on the bottom surface of the substrate, wherein the third conductive layer comprises a third signal net and a fourth signal net, the fourth signal net is electrically connected to the second signal net through a first via hole formed in the substrate.

3. The printed circuit board of claim 2 , wherein the third signal net is electrically connected to the first signal net through a second via hole formed in the substrate.

4. The printed circuit board of claim 1 , further comprising a reference plane embedded in substrate wherein the reference plane is able to provide one of the ground potential and the power potential.

5. The printed circuit board of claim 4 , wherein the reference plane is electrically connected to the second signal net by a via hole formed in the substrate.

6. The printed circuit board of claim 1 , wherein the second conductive layer comprises metal sheet, conductive epoxy polymer conductive composite, or carbon printing.

7. The printed circuit board of claim 1 , wherein the second conductive layer is electrically connected to the second signal net by one of a solder and conductive adhesive.

8. The printed circuit board of claim 1 , wherein the second signal net further comprises a trace, plane, pad, or finger.

9. The printed circuit board of claim 1 , further comprising an insulating cap layer covering the second conductive layer.

10. The printed circuit board of claim 1 , wherein the thickness of second conductive layer is less than or equal to 100 μm.

11. The printed circuit board of claim 1 , wherein the second conductive layer is filled into the openings to electrically connect to both the second signal nets.

12. The printed circuit board of claim 1 , wherein a top portion of the outermost insulating layer is made of the same material as a bottom portion of the outermost insulating layer.

13. The printed circuit board of claim 1 , wherein a spacing between the first conductive layer and the second conductive layer is between 50 μm to 350 μm.

14. The printed circuit board of claim 1 , wherein the outermost insulating layer fully covers the first signal nets.

15. A printed circuit board, comprising: a substrate having a top surface and a bottom surface;
a first conductive layer disposed on the top surface of the substrate, wherein the first conductive layer is in contact with the substrate and comprises three first signal nets, and two second signal nets, one on the left of the first signal nets, and the other on the right of the first signal nets;
an outermost insulating layer disposed on the top surface of the substrate to cover the substrate and the first conductive layer, wherein the outmost insulating layer is in contact with the substrate and comprises openings to fully expose a top and sides of both the second signal nets;
a second conductive layer disposed on the outermost insulating layer and substantially covering at least a portion of the first signal nets, including the exposed tops and sides of the second and third signal nets, wherein the second conductive layer which is able to provide one of a ground potential and a power potential is electrically connected to both the second signal nets through the openings; and
a third conductive layer disposed completely under the bottom surface of the substrate, wherein the first signal nets are disposed between the second signal nets, and the second signal nets comprises a via hole which is exposed from the openings,
wherein the entirety of the first conductive layer is disposed on the top surface of the substrate, and some of the top surface of the substrate is not covered by the first conductive layer.

16. The printed circuit board of claim 15 , wherein the second conductive layer and the third conductive layer serve as reference planes to suppress crosstalk noise.

17. The printed circuit board of claim 15 , wherein a spacing between the first conductive layer and the second conductive layer is between 50 μm to 350 μm.

18. A printed circuit board, comprising:
a substrate having a top surface and a bottom surface;
a first conductive layer disposed on the top surface of the substrate, wherein the first conductive layer is in contact with the substrate and comprises three first signal nets, and two second signal nets, one on the left of the first signal nets, and the other on the right of the first signal nets;
an outermost insulating layer disposed on the top surface of the substrate to cover the substrate and the first conductive layer, wherein the outmost insulating layer is in contact with the substrate and comprises openings to fully expose a top and sides of both the second signal nets; and
a second conductive layer disposed on the outermost insulating layer and covering a portion of the first signal nets, including the exposed tops and sides of both the second nets;
an insulating cap layer disposed on the second conductive layer, wherein the second conductive layer which is able to provide one of a ground potential and a power potential is electrically connected to both the second signal nets through the openings,
wherein a portion of the outermost insulating layer is uncovered by the second conductive layer, and the portion of the outermost insulating layer, which is thinner than the substrate, is uncovered by the insulating cap layer, and the insulating cap layer is wider than the second conductive layer and narrower than the outermost insulating layer,
wherein the first signal nets are disposed between the second signal nets, and the second signal nets comprises a via hole which is exposed from the openings,
wherein the entirety of the first conductive layer is disposed on the top surface of the substrate, and some of the top surface of the substrate is not covered by the first conductive layer.

19. The printed circuit board of claim 18 , wherein a portion of the second conductive layer is sandwiched between a sidewall of the openings and the at least one side of the second signal net.

Assignees

• Chen Nan Jang
• Mediatek Inc

Inventors

• Chen Nan-Jang

Classifications

• H05K1/0224

  Patterned shielding planes, ground planes or power planes (H05K1/0253 takes precedence) · CPC title

• H05K2201/09236

  Parallel layout · CPC title

• H05K1/0219 Primary

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H01P3/08

  Microstrips; Strip lines · CPC title

• H05K2201/0715

  provided by an outer layer of PCB · CPC title