Magnetically differential loop filter capacitor elements and methods related to same

Patent metadata

Field	Value
Publication number	US-9948313-B1
Application number	US-201615383483-A
Country	US
Kind code	B1
Filing date	Dec 19, 2016
Priority date	Dec 19, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Apparatus and methods are disclosed that utilize magnetically differential loop filter capacitor elements that are physically positioned adjacent voltage-controlled oscillator (VCO) inductor/s in the device layout of a phase locked loop (PLL) circuit. Such a PLL circuit may be employed, for example, to produce a PLL output signal for RF receivers, RF transmitters, RF transceivers and any other type of circuit configured to utilize a PLL output signal having a phase that is based on the phase of an input signal.

First claim

What is claimed is:

1. An apparatus having semiconductor device circuitry comprising:
at least one loop filter coupled to provide a control signal based on a frequency of an input signal, the loop filter comprising at least one capacitor coupled between the control signal and ground of the circuitry; and
a voltage controlled oscillator (VCO) comprising at least one inductor loop, the VCO being coupled to receive the control signal and to provide an output signal having a frequency that is a function of the control signal received from the loop filter;
where the loop filter capacitor comprises at least one capacitor element that includes spaced capacitor electrodes configured as a magnetically differential capacitor circuit.

2. The apparatus of claim 1 , where the spaced capacitor electrodes of the loop filter capacitor element are configured to create multiple component magnetic fields of opposite directions in response to the frequency of the input signal such that a composite magnetic field that results from the combination of the multiple component magnetic fields has a magnetic strength that is less than the magnetic strength of any of the component magnetic fields alone.

3. The apparatus of claim 1 , where the spaced capacitor electrodes of the loop filter capacitor element are interdigitated capacitor fingers.

4. The apparatus of claim 1 , where the spaced capacitor electrodes of the loop filter capacitor element have an axis of magnetically differential symmetry; and where the spaced capacitor electrodes of the loop filter capacitor element are configured to create opposing current dipole components on opposite sides of the axis of magnetically differential symmetry in response to the frequency of the input signal such that the magnetic fields created by the opposing current dipole components at least partially cancel each other out.

5. The apparatus of claim 1 , where the loop filter capacitor comprises multiple capacitor elements that each includes spaced capacitor electrodes configured as a magnetically differential capacitor circuit.

6. The apparatus of claim 1 , where the VCO inductor loop encloses a device area, and where at least a portion of the loop filter capacitor element is positioned within the device area enclosed by the VCO inductor loop.

7. The apparatus of claim 1 , where the VCO inductor loop encloses a device area, and where the entire loop filter capacitor element is positioned within the device area enclosed by the VCO inductor loop.

8. The apparatus of claim 1 , where the apparatus comprises phase locked loop (PLL) circuitry; and where the loop filter and VCO are components of the phase locked loop (PLL) circuitry.

9. The apparatus of claim 8 , where the apparatus is an RF apparatus that comprises an integrated circuit that includes the phase locked loop (PLL) circuitry.

10. A semiconductor circuit device, comprising:
a semiconductor substrate;
at least one capacitor element formed in one or more conductive layers on the semiconductor substrate, each of the conducive layers being separated from any other conductive layers by a layer of dielectric material, and the capacitor element including spaced capacitor electrodes configured in the conductive layers as a magnetically differential capacitor circuit; and
at least one conductive inductor loop formed in a different conductive layer on the semiconductor substrate that is separated from the conductive layers of the capacitor element by a layer of dielectric material, the inductor loop enclosing a device area of the semiconductor device;
where at least a portion of the capacitor element is positioned within the device area enclosed by the inductor loop.

11. The device of claim 10 , where the entire capacitor element is positioned within the device area enclosed by the inductor loop.

12. The device of claim 10 , where the at least one capacitor element comprises multiple capacitor elements coupled together, the multiple capacitor elements being entirely enclosed within the device area enclosed by the inductor loop.

13. The device of claim 10 , where the at least one capacitor element is formed in multiple conductive layers on the semiconductor substrate that are coupled together by conductive vias.

14. The device of claim 10 , further comprising a ground shield formed in a conductive layer between the semiconductor substrate and the conductive layers of the capacitor element.

15. The device of claim 10 , where the spaced capacitor electrodes are interdigitated capacitor fingers separated from each other by dielectric material.

16. A method, comprising:
using at least one loop filter to provide a control signal based on a frequency of an input signal, the loop filter comprising at least one capacitor coupled between the control signal and ground of the circuitry; and
using a voltage controlled oscillator (VCO) to receive the control signal and to provide an output signal having a frequency that is a function of the control signal received from the loop filter;
where the loop filter capacitor comprises at least one capacitor element that includes spaced capacitor electrodes configured as a magnetically differential capacitor circuit.

17. The method of claim 16 , further comprising providing the input signal to the loop filter to cause the spaced capacitor electrodes of the loop filter capacitor element to create multiple component magnetic fields of opposite directions that combine to form a composite magnetic field that has a magnetic strength that is less than the magnetic strength of any of the component magnetic fields alone.

18. The method of claim 16 , where the spaced capacitor electrodes of the loop filter capacitor element are interdigitated capacitor fingers.

19. The method of claim 16 , where the spaced capacitor electrodes of the loop filter capacitor element have an axis of magnetically differential symmetry; and where the method further comprises providing the input signal to the loop filter to cause the spaced capacitor electrodes of the loop filter capacitor element to create opposing current dipole components on opposite sides of the axis of magnetically differential symmetry in response to the frequency of the input signal such that the magnetic fields created by the opposing current dipole components at least partially cancel each other out.

20. The method of claim 16 , where the loop filter capacitor comprises multiple capacitor elements that each includes spaced capacitor electrodes configured as a magnetically differential capacitor circuit.

21. The method of claim 16 , where the VCO inductor loop encloses a device area, and where at least a portion of the loop filter capacitor element is positioned within the device area enclosed by the VCO inductor loop.

22. The method of claim 16 , where the VCO inductor loop encloses a device area, and where the entire loop filter capacitor element is positioned within the device area enclosed by the VCO inductor loop.

23. The method of claim 16 , where the loop filter and VCO are components of a phase locked loop (PLL) circuit; and where the method further comprises providing the VCO output signal to drive a divider to drive a signal generator of the PLL circuit.

24. The method of claim 23 , where the apparatus is an RF apparatus that comprises an integrated circuit that includes the phase locked loop (PLL) circuitry.

Assignees

• Silicon Lab Inc

Inventors

• Rafi Aslamali A

Classifications

• H01L28/60

  Electricity · mapped topic

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H10D1/692

  Electrodes · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title