Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
US9947829B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9947829-B2 |
| Application number | US-201113805273-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 27, 2011 |
| Priority date | Jun 24, 2010 |
| Publication date | Apr 17, 2018 |
| Grant date | Apr 17, 2018 |
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The present invention provides a substrate ( 1 ) with a bulk layer ( 3 ) and a buffer layer ( 4 ) having a thickness of less than 2 μm arranged on the bulk layer ( 3 ) for growth of a multitude of nanowires ( 2 ) oriented in the same direction on a surface ( 5 ) of the buffer layer ( 4 ). A nanowire structure, a nanowire light emitting diode comprising the substrate ( 1 ) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer ( 4 ).
Opening claim text (preview).
The invention claimed is: 1. A method for forming a structure comprising a plurality of nanowires oriented in the same direction, wherein the method comprises the steps of: providing a bulk layer; depositing a buffer layer with a thickness of less than 2 μm on the bulk layer, wherein the buffer layer is polycrystalline or amorphous and is formed by depositing two or more sub-layers, wherein the buffer layer is a non-epitaxial material selected from the group consisting of AlN and TiN, and combinations thereof, can withstand growth temperatures, and is grown with orientational properties that improve thermal properties of the structure; and growing one or more GaN nanowires on the buffer layer. 2. The method of claim 1 , wherein the deposition of the buffer layer preserves the orientation of the bulk layer. 3. The method of claim 1 , wherein the deposition of the buffer layer alters the orientation of the bulk layer. 4. The method of claim 1 , wherein the buffer layer or one or more of the sub-layers are deposited by LPCVD, APCVD or PECVD. 5. The method of claim 1 , wherein the buffer layer or one or more of the sub-layers are deposited by ALD. 6. The method of claim 1 , wherein the buffer layer or one or more of the sub-layers are deposited by PVD. 7. The method of claim 1 , wherein the buffer layer or one or more of the sub-layers are grown by MOVPE or HVPE. 8. The method of claim 1 , further comprising forming a masking layer on the buffer layer, forming holes in the masking layer, and growing one or more nanowires on the buffer layer through the holes. 9. The method of claim 1 , wherein the buffer layer does not comprise silicon nitride.
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