P-channel DEMOS device

Patent metadata

Field	Value
Publication number	US-9947783-B2
Application number	US-201615135154-A
Country	US
Kind code	B2
Filing date	Apr 21, 2016
Priority date	Apr 21, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

First claim

The invention claimed is:

1. A method of fabricating an integrated circuit (IC) having a p-channel drain extended metal oxide semiconductor (DEPMOS) device, comprising:
providing a substrate having a doped surface layer thereon;
forming at least one nwell finger defining a nwell length direction and an nwell width direction having nwell doping within said doped surface layer including a channel region;
forming a first pwell on one side of said nwell finger and a second pwell on an opposite side of said nwell finger;
forming a field dielectric layer on a portion of said doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along said width direction (WD boundary) that has said channel region therein;
forming a gate stack over said channel region including a gate dielectric layer and a patterned gate electrode on said gate dielectric layer, and
forming a p+ source in said first pwell and a p+ drain in said second pwell,
wherein said method includes reduced doping finger edge region processing which provides a reduced doping finger edge region including over a portion of said WD boundary within said nwell finger.

2. The method of claim 1 , wherein said field dielectric layer is formed by a Local Oxidation of Silicon (LOCOS) process.

3. The method of claim 1 , wherein said field dielectric layer is formed by a shallow trench isolation (STI) process including an etch and then a silicon oxide fill.

4. The method of claim 1 , wherein said reduced doping finger edge region processing comprises ion implantation of a p-type dopant to form said reduced doping finger edge region by counter doping.

5. The method of claim 4 , wherein said ion implantation comprises a boron dose between 1×10 12 and 1×10 13 cm −2 and an energy between 90 KeV and 200 KeV.

6. The method of claim 1 , wherein said wherein said reduced doping finger edge region processing uses a masking material in said reduced doping finger edge region during an n-type ion implant used to form said nwell finger.

7. The method of claim 1 , wherein said at least one nwell finger comprises a plurality of said nwell fingers.

8. The method of claim 1 , wherein said doped surface layer is doped ptype, wherein said forming said at least one nwell finger further comprises forming a first additional nwell beyond said first pwell opposite said nwell finger and a second additional nwell beyond said second pwell opposite said nwell finger, and
wherein said method further comprising forming an n-buried layer (NBL) and an n-type sinker in said substrate so that said first and said second additional nwells together with said NBL and said n-type sinker form an isolation tank.

Assignees

• Texas Instruments Inc

Inventors

• Tsai Chin-Yu
• Khan Imran
• Wu Xiaoju

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title