Dielectric isolated SiGe fin on bulk substrate

Patent metadata

Field	Value
Publication number	US-9947748-B2
Application number	US-201715406218-A
Country	US
Kind code	B2
Filing date	Jan 13, 2017
Priority date	Oct 6, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.

First claim

The invention claimed is:

1. A method for forming fins on a semiconductor device, comprising:
forming a first dielectric layer at bottoms of trenches in a substrate between first fins;
growing second fins of a material having a different composition than the substrate on sidewalls of the trenches;
recessing the second fins;
forming a second dielectric layer over the recessed second fins; and
removing the first fins by etching.

2. The method as recited in claim 1 , further comprising etching the trenches into a monocrystalline substrate and patterning a hardmask on the substrate wherein the hardmask controls a width and pitch of the second fins.

3. The method as recited in claim 1 , wherein forming the first dielectric layer includes filling the trenches with the first dielectric layer and recessing the first dielectric layer by etching to expose sidewalls of the first fins.

4. The method as recited in claim 1 , wherein the substrate includes silicon and the material having a different composition includes silicon germanium and growing the second fins includes epitaxially growing the second fins to form monocrystalline silicon germanium fins.

5. The method as recited in claim 4 , wherein the silicon germanium includes a germanium concentration of greater than 50%.

6. The method as recited in claim 1 , wherein the recessing of the second fins achieves a target fin height.

7. The method as recited in claim 1 , wherein the first dielectric layer is recessed to the bottoms of the trenches and remains to isolate the second fins from the substrate in a final structure.

8. A method for forming fins on a semiconductor device, comprising:
forming a first dielectric layer over a hardmask and in trenches in a substrate between first tins;
planarizing the first layer and stopping on the hardmask;
recessing the first dielectric layer into the trenches to form a dielectric pad at a bottom of the trenches and to expose sidewalls of the first fins;
growing second fins of a material having a different composition than the substrate on the sidewalk of the trenches;
forming a second dielectric layer over the second fins;
planarizing the second dielectric layer and stopping on the hardmask;
removing the hardmask; and
removing the first fins by etching.

9. The method as recited in claim 8 , further comprising patterning a hardmask on a monocrystalline substrate, wherein the hardmask controls a width and pitch of the second fins.

10. The method as recited in claim 8 , wherein the substrate includes silicon and the material having a different composition includes silicon germanium and growing the second fins includes epitaxially growing the second fins to form monocrystalline silicon germanium fins.

11. The method as recited in claim 10 , wherein the silicon germanium includes a germanium concentration of greater than 50%.

12. The method as recited in claim 8 , further comprising recessing the second fins to achieve a target fin height.

13. The method as recited in claim 8 , wherein the dielectric pad remains to isolate the second fins from the substrate in a final structure.

Assignees

• IBM
• Int Busines Machines Corporation

Inventors

• Bu Huiming
• Mochizuki Shogo
• Yamashita Tenko

Classifications

• H10P50/282

  of inorganic materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1912

  using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title