Ultralow power carbon nanotube logic circuits and method of making same

Patent metadata

Field	Value
Publication number	US-9947724-B2
Application number	US-201715437060-A
Country	US
Kind code	B2
Filing date	Feb 20, 2017
Priority date	Oct 11, 2013
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.

First claim

What is claimed is:

1. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) logic device with single-walled carbon nanotubes (SWCNTs), comprising:
forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate;
forming a plurality of contacts on the substrate;
depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one n-type metal-oxide-semiconductor (NMOS) transistor and at least one p-type metal-oxide semiconductor (PMOS) transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively;
depositing a first encapsulation layer on the substrate to cover the at least one PMOS transistor and the at least one NMOS transistor, wherein the first encapsulation layer is formed by a photoresist;
removing a part of the first encapsulation layer to expose the at least one NMOS transistor, such that remaining first encapsulation layer covers the at least one PMOS transistor; and
coating a second encapsulation layer to cover the exposed at least one NMOS transistor and the remaining first encapsulation layer, wherein the second encapsulation layer is formed by Al 2 O 3 ;
wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage; and
wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage V out .

2. The method of claim 1 , wherein each of the at least one PMOS transistor and each of the at least one NMOS transistor is a thin-film transistor (TFT).

3. The method of claim 1 , wherein the metal of each of the local metal gate structures is nickel (Ni).

4. The method of claim 3 , further comprising:
depositing a layer of Al 2 O 3 over the substrate to cover the Ni of each of the local metal gate structures.

5. The method of claim 1 , wherein said forming the plurality of contacts on the substrate comprises:
patterning the plurality of contacts on the substrate by photolithography.

6. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) logic device with single-walled carbon nanotubes (SWCNTs), comprising:
forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate;
forming a plurality of contacts on the substrate; and
depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one n-type metal-oxide-semiconductor (NMOS) transistor and at least one p-type metal-oxide semiconductor (PMOS) transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively;
wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage; and
wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage Vout; wherein said depositing the SWCNTs on the substrate comprises:
depositing the SWCNTs on a membrane;
stamping the membrane with the SWCNTs on the substrate; and
submerging the substrate with the membrane and the SWCNTs thereon in a solvent to dissolve the membrane.

7. The method of claim 6 , wherein the solvent is acetone.

8. The method of claim 6 , wherein said depositing the SWCNTs on the substrate further comprises:
covering a plurality of channel areas of the SWCNTs on the substrate with a photoresist; and
etching the SWCNTs outside at least one of the channel areas by reactive ion etching.

9. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) logic device with single-walled carbon nanotubes (SWCNTs), comprising:
forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate;
forming a plurality of contacts on the substrate; and
depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one n-type metal-oxide-semiconductor (NMOS) transistor and at least one p-type metal-oxide semiconductor (PMOS) transistor, wherein each of the at least one NMOS transistor and each of the at least one PMOS transistor has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively;
wherein the gate of each of the at least one PMOS transistor and the gate of each of the at least one NMOS transistor is configured to alternatively receive at least one input voltage; and
wherein at least one of the drain of the at least one PMOS transistor and the drain of the at least one NMOS transistor is configured to output an output voltage Vout;
wherein said doping the certain area of the SWCNTs comprises:
annealing the substrate in vacuum at an annealing temperature for a period of time; and depositing a benzyl viologen solution onto the certain area of the SWCNTs to form the at least one NMOS transistor.

10. The method of claim 9 , wherein the annealing temperature is about 200° C., and the period of time is about 1 hour.

11. The method of claim 6 , wherein the CMOS logic device is a logic inverter.

12. The method of claim 11 , wherein
the at least one PMOS transistor comprises a first PMOS thin-film transistor (TFT);
the at least one NMOS transistor comprises a first NMOS TFT;
the at least one input voltage comprises a common input voltage V IN ;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a common input voltage line for alternatively receiving the common input voltage V IN ;
the drain of the first PMOS TFT and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for alternatively outputting the output voltage V OUT ;
the source of the first PMOS TFT is connected to a power supply V DD ; and
the source of the first NMOS TFT is connected to ground.

13. The method of claim 12 , wherein the CMOS logic device a low noise margin (NM) of about 0.32 V DD , and a high NM of about 0.54 V DD .

14. The method of claim 6 , wherein the CMOS logic device is a logic NAND gate.

15. The method of claim 14 , wherein
the at least one PMOS transistor comprises a first PMOS thin-film transistor (TFT) and a second PMOS TFT;
the at least one NMOS transistor comprises a first NMOS TFT and a second NMOS TFT;
the at least one input voltage comprises a first input voltage V A and a second input voltage V B ;
the gate of the first PMOS TFT and the gate of the first NMOS TFT are respectively electrically connected to a first common input voltage line for alternatively receiving the first input voltage V A ;
the gate of the second PMOS TFT and the gate of the second NMOS TFT are respectively electrically connected to a second common input voltage line for alternatively receiving the second input voltage V B ;
the drain of the first PMOS TFT, the drain of the second PMOS TFT, and the drain of the first NMOS TFT are respectively electrically connected to a common output voltage line for outputtin

Assignees

• Univ Northwestern
• Univ Minnesota

Inventors

• Hersam Mark C
• Geier Michael L
• Prabhumirashi Pradyumna L
• Xu Weichao
• Kim Hyungil

Classifications

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H01L51/107

  Electricity · mapped topic

• H01L51/055

  Electricity · mapped topic

• H01L51/0048

  Electricity · mapped topic

• H01L51/0023

  Electricity · mapped topic