Low temperature polycrystalline silicon TFT array substrate and method of producing the same, display apparatus

Patent metadata

Field	Value
Publication number	US-9947697-B2
Application number	US-201414769891-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Jun 30, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

First claim

What is claimed is:

1. A method for producing a low temperature polycrystalline silicon field effect thin film transistor array substrate, comprising the steps of: a) using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; b) forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; c) forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; d) forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence on the etched metal layer and using stepped patterning and peeling processes to pattern the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode; e) forming a pixel definition layer on the pixel electrode to finalize the production of the low temperature polycrystalline silicon field effect thin film transistor array substrate; wherein the step a) comprises: cleaning the substrate to deposit a layer of SiN film and a layer of Si0 2 film sequentially on a surface of the substrate, the SiN film and the Si0 2 film constituting a buffer layer; depositing a layer of amorphous silicon film on the buffer layer, dehydrogenating the amorphous silicon film and crystallizing the amorphous silicon film to form the polycrystalline silicon film; cleaning the polycrystalline silicon film and using a semi-transparent mask to form a first layer of photo resist ( 5 a ) and a second layer of photo resist ( 5 b ) with different thicknesses on a surface of the polycrystalline silicon film, the thickness of the first layer of photo resist ( 5 a ) being greater than that of the second layer of photo resist ( 5 b ); etching the polycrystalline silicon film to form a film for constituting the polycrystalline silicon active layer and a film for constituting the lower polar plate of the polycrystalline silicon storage capacitor, and then removing the second layer of photo resist ( 5 b ) while retaining the first layer of photo resist ( 5 a ) as an ion-implantation barrier layer, doping the film for constituting the lower polar plate of the polycrystalline silicon storage capacitor with ions, and then removing the first layer of photo resist ( 5 a ) so as to form the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor on the substrate simultaneously.

2. The method according to claim 1 , wherein the SiN film and the Si0 2 film constituting the buffer layer have a thickness of 50 nm˜100 nm and a thickness of 100 nm˜400 nm, respectively; the amorphous silicon film deposited on the buffer layer has a thickness of 40 nm˜100 nm, wherein the amorphous silicon film is dehydrogenated by a heat treatment furnace and crystallized by laser annealing crystallization, metal induced crystallization or solid phase crystallization; the semi-transparent mask is a half-tone or gray-tone mask; the first layer of photo resist ( 5 a ) has a thickness of 1-3 micrometers and covers a region of the polycrystalline silicon film for forming the polycrystalline silicon active layer; and the second layer of photo resist ( 5 b ) has a thickness of 0.5-1 micrometer and covers a region of the polycrystalline silicon film for forming the lower polar plate of the polycrystalline silicon storage capacitor; etching the polycrystalline silicon film by a plasma process or an inductance coupling plasma process; removing the second layer of photo resist ( 5 b ) by a plasma ashing process while retaining the first layer of photo resist ( 5 a ) as the ion-implantation barrier layer; doping the film for constituting the lower polar plate of the polycrystalline silicon storage capacitor with ions by an ion implantation process or an ion cloud implantation process, wherein the doping ions are PH3/H2 or B2H6/H2, with an ion implantation dose of 1014 ions/cm2-1016 ions/cm2 and an ion implantation energy of 10 KeV˜100 KeV.

3. The method according to claim 1 , wherein in the step b), the gate insulation layer is formed on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline storage capacitor by a plasma enhanced chemical vapor deposition process, the gate insulation layer being composed of the SiO 2 film and the SiN film formed above the SiO 2 film, the SiO 2 film having a thickness of 30 nm˜100 nm and the SiN film having a thickness of 20 nm˜100 nm.

4. The method according to claim 3 , wherein the gate insulation layer deposited on the lower polar plate of the polycrystalline silicon storage capacitor is configured to constitute an insulation medium of the polycrystalline storage capacitor.

5. The method according to claim 1 , wherein in the step c), the step of forming the metal layer on the gate insulation layer comprises depositing a layer of metal film with a thickness of 200 nm˜500 nm on the gate insulation layer by a magnetron sputtering process, and then removing the part of the metal film in the region other than the gate electrode, the gate lines, the source electrode, the drain electrode and the data lines by lithographic and etching processes to form the gate electrode, the gate lines connected with the gate electrode, the source electrode, the drain electrode and the data lines connected with the source electrode and the drain electrode, as well an upper polar plate of the polycrystalline silicon storage capacitor.

6. The method according to claim 5 , wherein the metal film is a single-layer metal film composed of Al, Cu, Mo, Ti or AlNd, or a multi-layer metal film composed of Mo/Al/Mo or Ti/Al/Ti;
the data lines connected with the source electrode and the drain electrode are formed by continuous line-shaped metal films, the gate lines are formed by discontinuous line-shaped metal films, and the gate lines are interrupted at crossings of them with the data lines;
the step of etching the metal layer is performed by a wet or dry eroding process;
the lower polar plate of the polycrystalline silicon storage capacitor, the gate insulation layer formed on the lower polar plate of the polycrystalline silicon storage capacitor and an upper polar plate of the polycrystalline silicon storage capacitor constitute the polycrystalline silicon storage capacitor.

7. The method according to claim 1 , wherein the step d) comprises:
depositing a layer of medium film on the gate electrode, the source electrode, the drain electrode, the metal gate lines and the data lines by plasma enhanced chemical vapor deposition to form the passivation layer, and then performing a rapid thermal annealing process or heat treatment furnace annealing process to hydrogenate the interior of the polycrystalline silicon active layer and the interface between the polycrystalline silicon film and the SiO 2 film by using the SiN film in the passivation layer and the gate insulation layer;
forming a third layer of photo resist ( 5 c ) and a fourth layer of photo resist ( 5 d ) with different thicknesses on a surface of the passivation layer by means of a semi-transparent mask, the thickness of the third layer of photo resist ( 5 c ) being greater than that of the fourth layer of photo resist ( 5 d );
etching the passivation layer and the gate insulation layer under the passivation layer by a plasma process or inductance coupling plasma process to form a passivation layer via hole;
removing

Assignees

• Boe Technology Group Co Ltd

Inventors

• Long Chunping
• Liang Yinan
• Liu Zheng
• Wang Zuqiang
• Tian Xueyan

Classifications

• H01L27/1288 Primary

  Electricity · mapped topic

• H01L27/3262

  Electricity · mapped topic

• H01L2227/323

  Electricity · mapped topic

• H01L27/1255

  Electricity · mapped topic

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title