Integrated circuits with components on both sides of a selected substrate and methods of fabrication

Patent metadata

Field	Value
Publication number	US-9947688-B2
Application number	US-201213528832-A
Country	US
Kind code	B2
Filing date	Jun 20, 2012
Priority date	Jun 22, 2011
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

First claim

What is claimed is:

1. A method for forming integrated circuits (ICs) from a semiconductor wafer including an active layer, a buffer layer for improved electrical isolation between electronic components, and a silicon substrate, a first surface of the buffer layer coupled to the active layer, and a second, opposite surface of the buffer layer coupled to the silicon substrate, comprising:
a) forming a first circuit layer of active and/or passive electronic components in the active layer of the semiconductor wafer;
b) removing the silicon substrate from the semiconductor wafer to expose the second surface of the buffer layer;
c) coupling the second surface of the buffer layer to a first surface of a monolithic insulating substrate suitable for forming active and/or passive electronic components; and,
d) forming a second circuit layer of active and/or passive electronic components on a second, opposite surface of the insulating substrate.

2. The method of claim 1 , wherein the insulating substrate comprises a material selected from the following types of materials: sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide, sintered silicon carbide, CVD silicon carbide, and alumina.

3. The method of claim 1 , wherein the insulating substrate comprises sapphire, and wherein the second circuit layer comprises only passive electronic components.

4. The method of claim 1 , wherein the insulating substrate comprises a piezoelectric material, and wherein the second circuit layer comprises acoustic wave electronic components.

5. The method of claim 1 , further comprising thinning the insulating substrate subsequent to coupling the second surface of the buffer layer to the first surface of the insulating substrate and prior to forming the second circuit layer on the second surface of the insulating substrate.

6. The method of claim 1 , further comprising:
a) forming contact elements on the first circuit layer; and,
b) separating the ICs into dies, each die comprising an IC.

7. A method for forming integrated circuits (ICs) from a semiconductor wafer including an active layer, a buffer layer for improved electrical isolation between electronic components, and a silicon substrate, a first surface of the buffer layer coupled to the active layer, and a second, opposite surface of the buffer layer coupled to the silicon substrate, comprising:
a) forming a first circuit layer of active and/or passive electronic components in the active layer of the semiconductor wafer;
b) removing the silicon substrate from the semiconductor wafer to expose the second surface of the buffer layer;
c) forming a second circuit layer of active and/or passive electronic components on a second surface of a monolithic insulating substrate suitable for forming active and/or passive electronic components; and,
d) after forming the second circuit layer, coupling the second surface of the buffer layer to a first, opposite surface of the insulating substrate.

8. The method of claim 7 , wherein the insulating substrate comprises a material selected from the following types of materials: sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

9. The method of claim 7 , wherein the insulating substrate comprises sapphire, and wherein the second circuit layer comprises only passive electronic components.

10. The method of claim 7 , wherein the insulating substrate comprises a piezoelectric material, and wherein the second circuit layer comprises acoustic wave electronic components.

11. The method of claim 7 , further comprising thinning the insulating substrate subsequent to forming the second circuit layer on the second surface of the insulating substrate and prior to coupling the second surface of the buffer layer to the first surface of the insulating substrate.

12. The method of claim 7 , further comprising:
a) forming contact elements on the first circuit layer; and,
b) separating the ICs into dies, each die comprising an IC.

13. A method for forming integrated circuits (ICs) from a semiconductor wafer including an active layer, a buffer layer for improved electrical isolation between electronic components, and a silicon substrate, a first surface of the buffer layer coupled to the active layer, and a second, opposite surface of the buffer layer coupled to the silicon substrate, comprising:
a) forming a first circuit layer of active and/or passive electronic components in the active layer of the semiconductor wafer;
b) removing the silicon substrate from the second surface of the buffer layer;
c) forming a second circuit layer of active and/or passive electronic components on a second substrate suitable for forming active and/or passive electronic components;
d) separating the second circuit layer from the second substrate;
e) coupling the second surface of the buffer layer to a first surface of an insulating substrate; and,
f) coupling the second circuit layer to a second surface of the insulated substrate.

14. The method of claim 13 , wherein the insulating substrate comprises a material selected from the following types of materials: sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

15. The method of claim 13 , wherein the second substrate is selected from the following: a silicon-on-insulator (SOI) substrate, a silicon substrate having an insulating top layer, and a piezoelectric substrate.

16. The method of claim 15 , wherein the insulating top layer comprises silicon dioxide.

17. The method of claim 13 , wherein the second circuit layer comprises only at least one of the following types of electronic components: active components, passive components, opto-electronic components, microelectromechanical components, and acoustic wave components.

18. The method of claim 13 , further comprising thinning the insulating substrate subsequent to coupling the second surface of the buffer layer to the first surface of the insulating substrate and prior to coupling the second circuit layer to the second surface of the insulating substrate.

19. The method of claim 13 , further comprising:
a) forming contact elements on the first circuit layer; and,
b) separating the ICs into dies, each die comprising an IC.

20. A method for forming integrated circuits (ICs) from a semiconductor wafer including an active layer, a buffer layer for improved electrical isolation between electronic components, and a silicon substrate, a first surface of the buffer layer coupled to the active layer, and a second, opposite surface of the buffer layer coupled to the silicon substrate, comprising:
a) forming a first circuit layer of active and/or passive electronic components in the active layer of the semiconductor wafer;
b) removing the silicon substrate from the second surface of the buffer layer;
c) forming a second circuit layer of active and/or passive electronic components on a second substrate suitable for forming active and/or passive electronic components;
d) separating the second circuit layer from the second substrate;
e) coupling the second circuit layer to a second surface of an insulating substrate; and,
f) after coupling the second circuit layer to the second surface of the insulating substrate, coupling the second surface of the buffer layer to a first surface of the insulating substrate.

Assignees

• Cable James S
• Miscione Anthony Mark
• Reedy Ronald Eugene
• Psemi Corp

Inventors

• Cable James S
• Miscione Anthony Mark
• Reedy Ronald Eugene

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/01204

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title