Semiconductor device structures including buried digit lines and related methods

Patent metadata

Field	Value
Publication number	US-9947666-B2
Application number	US-201213354957-A
Country	US
Kind code	B2
Filing date	Jan 20, 2012
Priority date	Jan 20, 2012
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

First claim

What is claimed is:

1. A method of forming a conductive connection in a semiconductor device, comprising:
forming columns of substrate material;
forming at least one buried metal digit line at least partially within undercut regions of the columns of substrate material;
forming an upwardly extending protrusion of the at least one buried metal digit line at an end thereof; and
directly connecting a metal contact to the upwardly extending protrusion of the at least one buried metal digit line.

2. The method of claim 1 ,
wherein forming the upwardly extending protrusion of the at least one buried metal digit line at an end thereof comprises forming the upwardly extending protrusion to extend along one of the columns of substrate material.

3. A method for forming a semiconductor device structure, the method comprising:
forming a plurality of trenches in a substrate, each trench extending horizontally into an array region and into a buried digit line end region;
forming buried digit lines comprising a metal material in the plurality of trenches over sidewalls of columns of substrate material between the plurality of trenches;
filling the plurality of trenches with a mask material to cover the metal material;
removing mask material from the plurality of trenches in the array region to expose a portion of the metal material;
removing the exposed portion of the metal material in the array region;
forming a plurality of conductive contacts comprising a metal over the columns of the substrate material in between the plurality of trenches and in direct physical contact with metallic connections comprising the metal material of the buried digit lines in the buried digit line end region, the metallic connections disposed between a respective buried digit line and an associated conductive contact; and
at least partially filling the plurality of trenches with a dielectric material separating adjacent columns of the substrate material.

4. The method of claim 3 , further comprising removing material from the substrate to extend a depth of the plurality of trenches into the substrate and to form horizontally recessed regions along the sidewalls of the plurality of trenches before forming the metal material.

5. The method of claim 4 , wherein forming the metal material comprises forming the metal material at least partially within the horizontally recessed regions.

6. The method of claim 3 , further comprising:
removing portions of the metal material to separate the metal material along opposing sidewalls of each trench; and
vertically recessing the metal material a distance between about 0 nm and about 20 nm from an upper surface of the substrate.

7. The method of claim 6 , wherein removing portions of the metal material comprises removing portions of the metal material from horizontal surfaces of the substrate.

8. The method of claim 3 , further comprising covering the mask material with a photolithographic mask in the buried digit line end region to inhibit removal of the mask material from the buried digit line end region.

9. The method of claim 3 , wherein forming a plurality of conductive contacts comprises forming each conductive contact of the plurality of conductive contacts to touch the metal material on two sidewalls.

10. A method for forming a buried digit line contact, the method comprising:
removing a portion of a substrate to form trenches defined by sidewalls of columns of the substrate, the trenches extending horizontally in an array region and in a buried digit line end region of the substrate;
forming a metal material on the sidewalls and in the trenches in the array region and in the buried digit line end region; and
removing a portion of the metal material from within the trenches in the array region to form a plurality of buried digit lines;
forming a plurality of metal conductive contacts over the columns of the substrate to physically contact metallic connections comprising the metal material in the buried digit line end region, the metallic connections disposed between a respective metal conductive contact and a buried digit line; and
at least partially filling the trenches with a dielectric material separating adjacent columns of the substrate.

11. The method of claim 10 , further comprising leaving another portion of the metal material in horizontally recessed sidewall regions of the trenches.

12. The method of claim 11 , further comprising partially filling the trenches in the array region with a mask material to cover the another portion of the metal material.

13. The method of claim 11 , further comprising covering the metal material in the buried digit line end region to inhibit removal thereof.

14. The method of claim 13 , further comprising inhibiting removal of a portion of the metal material along the sidewalls in the buried digit line end region with the mask formed over the metal material in the buried digit line end region while the portion of the metal material is removed from within the trenches in the array region.

15. A memory device, comprising:
a substrate including trenches extending horizontally in an array region and a buried digit line end region, the trenches at least partially filled with a dielectric material separating adjacent columns of substrate material;
buried digit lines comprising a metal material in the trenches along sidewalls of the columns of substrate material;
conductive contacts comprising a metal over the columns of substrate material in the buried digit line end region; and
metallic connections comprising the metal material of the buried digit lines, each metallic connection disposed between and physically contacting a buried digit line and a conductive contact.

16. The memory device of claim 15 , wherein the metallic connections are each integral with an associated buried digit line.

17. The memory device of claim 15 , wherein each conductive contact physically contacts two metallic connections.

18. The memory device of claim 15 , wherein the buried digit lines are disposed at least partially within undercut regions of the columns of substrate material.

19. The memory device of claim 15 , further comprising doped regions in the substrate, wherein each buried digit line is in electrical contact with a doped region.

20. The memory device of claim 15 , wherein an upper surface of each metallic connection is proximate an upper surface of an associated column of substrate material.

21. The memory device of claim 15 , wherein an upper surface of each metallic connection is vertically recessed from an upper surface of an associated column of substrate material a distance between about 0 nm and about 20 nm.

22. A semiconductor device structure, comprising:
buried metal digit lines in a substrate;
columns of a substrate material, wherein the buried metal digit lines are disposed at least partially within undercut regions of the columns of substrate material; and
metal contacts above and connected to metal of the buried metal digit lines at ends of the buried metal digit lines.

23. The semiconductor device structure of claim 22 , further comprising a metal material comprising the metal of the buried metal digit lines between and connecting each buried metal digit line and an associated metal contact.

24. The semiconductor device structure of claim 23 , wherein the metal material is disposed along the columns of the substrate material, the metal material extending from

Assignees

• Surthi Shyam
• Mathew Suraj
• Micron Technology Inc

Inventors

• Surthi Shyam
• Mathew Suraj

Classifications

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L21/743

  Electricity · mapped topic

• H01L21/76897

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic