Flip chip cavity package

US9947605B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9947605-B2
Application numberUS-91469410-A
CountryUS
Kind codeB2
Filing dateOct 28, 2010
Priority dateSep 4, 2008
Publication dateApr 17, 2018
Grant dateApr 17, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages.

First claim

Opening claim text (preview).

What is claimed is: 1. A process for forming a semiconductor package comprising: a. forming a leadframe strip having a first cavity formed on a first face opening to a second cavity formed on a second face; b. at least partially encasing the leadframe strip in a first mold compound thereby forming a molded leadframe strip with external surfaces of the first mold compound and the leadframe strip substantially coplanar; c. mounting at least one flip chip semiconductor device on the molded leadframe strip with the at least one flip chip semiconductor device positioned, in cross section, over only one contiguous cavity, a combination of the first cavity on the first face of the leadframe strip and the second cavity on the second face, the at least one flip chip semiconductor device having conductive masses attached thereon to effectuate electrical contact between the at least one flip chip semiconductor device and the molded leadframe strip; d. dispensing liquid encapsulant on the at least one flip chip semiconductor device to form a third cavity unfilled with any solid compound between the at least one flip chip semiconductor device and the molded leadframe strip in cross section; e. at least partially encasing the molded leadframe strip, the at least one flip chip semiconductor device, and the conductive masses in a second mold compound, wherein the second mold compound is molded such that a top surface of the flip chip semiconductor device is substantially exposed and uncovered by the second mold compound in cross section and the entire sides of the flip chip semiconductor device are encased by the liquid encapsulant in cross section; and f. singulating the molded leadframe strip to form discrete semiconductor packages. 2. The process in claim 1 , wherein the second mold compound is dispensed to produce a globular form on the at least one flip chip semiconductor device to form the cavity between the at least one flip chip semiconductor device and the at least one molded leadframe. 3. The process in claim 1 , wherein the conductive masses are formed in a shape of one of substantially spherical or substantially cylindrical. 4. The process in claim 1 , further comprising embossing at least one step cavity having contact precipices into the molded leadframe strip for receiving the at least one flip chip semiconductor device. 5. The process of claim 1 , wherein the first and second mold compounds comprise the same material. 6. The process of claim 1 , wherein the first and second mold compounds comprise differing material. 7. The process in claim 1 , wherein the conductive masses are formed in a shape that is substantially cylindrical. 8. The process in claim 1 , wherein the process further comprises mounting a first surface of the first leadframe strip on an adhesive side of an adhesive tape and mounting a second surface of the first leadframe strip to a non-adhesive tape. 9. The process of claim 8 , wherein the process further comprises removing the adhesive tape and the non-adhesive tape from the molded leadframe strip. 10. The process of claim 1 , wherein the process further comprises mounting a first surface of the first leadframe strip on a first non-adhesive tape and mounting a second surface of the first leadframe strip to a second non-adhesive tape. 11. A process for forming a semiconductor package comprising: a. forming a leadframe strip having a first cavity formed on a first face opening to a second cavity formed on a second face; b. at least partially encasing the leadframe strip in a first mold compound thereby forming a molded leadframe strip with external surfaces of the first mold compound and the leadframe strip substantially coplanar; c. mounting at least one flip chip semiconductor device on the molded leadframe strip with the at least one flip chip semiconductor device positioned, in cross section, over only one contiguous cavity, a combination of the first cavity on the first face of the leadframe strip and the second cavity on the second face, the at least one flip chip semiconductor device having conductive masses attached thereon to effectuate electrical contact between the at least one flip chip semiconductor device and the molded leadframe strip; d. at least partially encasing the molded leadframe strip, the at least one flip chip semiconductor device, and the conductive masses in a second mold compound forming a third cavity between the at least one flip chip semiconductor device and the molded leadframe strip, wherein in cross section containing the conductive masses the third cavity is unfilled with any solid compound within the third cavity, wherein the entire sides of the flip chip semiconductor device are encased by the second mold compound in cross section; and e. singulating the molded leadframe strip to form discrete semiconductor packages. 12. A process for forming a semiconductor package comprising: a. forming a leadframe strip having a first cavity formed on a first face opening to a second cavity formed on a second face; b. at least partially encasing the leadframe strip in a first mold compound thereby forming a molded leadframe strip with external surfaces of the first mold compound and the leadframe strip substantially coplanar; c. mounting at least one flip chip semiconductor device on the molded leadframe strip, the at least one flip chip semiconductor device having conductive masses attached thereon to effectuate electrical contact between the at least one flip chip semiconductor device and the molded leadframe strip; d. at least partially encasing the molded leadframe strip, the at least one flip chip semiconductor device, and the conductive masses in a second mold compound, forming a third cavity between the at least one flip chip semiconductor device and the molded leadframe strip, wherein in cross section containing the plurality of conductive masses the third cavity is unfilled with any solid compound within the third cavity; and e. singulating the molded leadframe strip to form discrete semiconductor packages. 13. The process in claim 12 , wherein the second mold compound is dispensed to produce a globular form on the at least one flip chip semiconductor device to form the third cavity between the at least one flip chip semiconductor device and the at least one molded leadframe. 14. The process in claim 12 , further comprising embossing at least one step cavity having contact precipices into the molded leadframe strip for receiving the at least one flip chip semiconductor device. 15. The process of claim 12 , wherein the first and second mold compounds comprise the same material. 16. The process of claim 12 , wherein the first and second mold compounds comprise differing material. 17. The process in claim 12 , wherein the conductive masses are formed in a shape of one of substantially spherical or substantially cylindrical. 18. The process in claim 12 , wherein the process further comprises mounting a first surface of the first leadframe strip on an adhesive side of an adhesive tape and mounting a second surface of the first leadframe strip to a non-adhesive tape. 19. The process of claim 18 , wherein the process further comprises removing the adhesive tape and the non-adhesive tape from the molded leadframe strip. 20. The process of claim 12 , wherein the process further comprises mounting a first surface of the first leadframe strip on a first non-adhesive tape and mounting a second surface of the first leadframe strip to a second non-adhesive tape.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • batch processes · CPC title

  • Die-attach connectors and bond wires · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • of bump connectors · CPC title

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Frequently asked questions

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What does patent US9947605B2 cover?
A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached …
Who is the assignee on this patent?
Sirinorakul Saravuth, Nondhasitthichai Somchai, Utac Headquarters Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W74/111. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).