Integrated superconductor device and method of fabrication

Patent metadata

Field	Value
Publication number	US-9947441-B2
Application number	US-201314077901-A
Country	US
Kind code	B2
Filing date	Nov 12, 2013
Priority date	Nov 12, 2013
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

An integrated superconductor device may include a substrate base and an intermediate layer disposed on the substrate base and comprising a preferred crystallographic orientation. The integrated superconductor device may further include an oriented superconductor layer disposed on the intermediate layer and a conductive strip disposed on a portion of the oriented superconductor layer, The conductive strip may define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region.

First claim

What is claimed is:

1. An integrated superconductor device, comprising:
a substrate base formed of glass;
an intermediate layer disposed on the substrate base, the intermediate layer having a preferred crystallographic orientation and comprising a layer of silicon nitride, a first layer of MgO disposed on the layer of silicon nitride, and a separate, second layer of MgO disposed on the first layer of MgO, the second layer of MgO having a higher degree of crystalline orientation relative to the first layer of MgO;
an oriented superconductor layer disposed on the intermediate layer; and
a conductive strip disposed on a portion of the oriented superconductor layer to define a superconductor region of the oriented superconductor layer thereunder, and an exposed region of the oriented superconductor layer adjacent the superconductor region;
wherein the conductive strip defines a serpentine pattern.

2. The integrated superconductor device of claim 1 , wherein the substrate comprises a first side and a second side, wherein the conductive strip is deposited on the first side, the integrated superconductor device further comprising:
a second intermediate layer disposed on the substrate base on the second side, the second intermediate layer comprising a preferred crystallographic orientation;
a second oriented superconductor layer disposed on the second intermediate layer; and
a second conductive strip disposed on a portion of the second oriented superconductor layer to define a second superconductor region of the second oriented superconductor layer thereunder, and a second exposed region of the second oriented superconductor layer adjacent the second superconductor region, wherein the second conductive strip is electrically connected to the first conductive strip.

3. The integrated superconductor device of claim 2 , wherein the first and second conductive strip comprise a bifilar wound structure.

4. The integrated superconductor device of claim 3 , wherein the first and second conductive strip are bifilar with respect to one another.

5. The integrated superconductor device of claim 1 , wherein the exposed region of the oriented superconductor layer comprises a defective superconductor material that is a non-superconductor.

6. The integrated superconductor device of claim 1 , wherein the oriented superconductor layer comprises RBa 2 Cu 3 O 7-x where R is a rare earth element.

7. The integrated superconductor device of claim 1 , further comprising a protective coating disposed on the conductive strip and exposed region.

Assignees

• Varian Semiconductor Equipment Ass Inc

Inventors

• Wang Connie P
• Murphy Paul
• Sullivan Paul

Classifications

• H01L39/249

  Electricity · mapped topic

• H01L39/2458

  Electricity · mapped topic

• H02H9/023

  Current limitation using superconducting elements · CPC title

• H01L39/143

  Electricity · mapped topic

• H01L39/2461

  Electricity · mapped topic