Electrically gated three-terminal circuits and devices based on spin hall torque effects in magnetic nanostructures apparatus, methods and applications

Patent metadata

Field	Value
Publication number	US-9947382-B2
Application number	US-201615357391-A
Country	US
Kind code	B2
Filing date	Nov 21, 2016
Priority date	Aug 6, 2012
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Three-terminal magnetic circuits and devices based on the spin-transfer torque (STT) effect via a combination of injection of spin-polarized electrons or charged particles by using a charge current in a spin Hall effect metal layer coupled to a free magnetic layer and application of a gate voltage to the free magnetic layer to manipulate the magnetization of the free magnetic layer for various applications, including nonvolatile memory functions, logic functions and others. The charge current is applied to the spin Hall effect metal layer via first and second electrical terminals and the gate voltage is applied between a third electrical terminal and either of the first and second electrical terminals. The spin Hall effect metal layer can be adjacent to the free magnetic layer or in direct contact with the free magnetic layer to allow a spin-polarized current generated via a spin Hall effect under the charge current to enter the free magnetic layer. The disclosed three-terminal magnetic circuits can also be applied to signal oscillator circuits and other applications.

First claim

What is claimed is:

1. An electronic device including a magnetic tunneling junction memory based on a three-terminal circuit configuration, comprising:
a memory module that includes (1) an array of memory cells arranged in rows and columns for storing data, (2) row and column conductive lines that coupled to the memory cells; and (3) a memory control circuit coupled to the array of memory cells and the row and column conductive lines to read or write data in the memory cells,
wherein each memory cell includes:
a magnetic tunneling junction (MTJ) that includes a pinned magnetic layer having a fixed magnetization direction, a free magnetic layer having a magnetization direction that is changeable, and a non-magnetic junction layer between the magnetic free layer and the pinned magnetic layer and formed of an insulator material sufficiently thin to allow tunneling of electrons between the magnetic free layer and the pinned magnetic layer;
a spin Hall effect metal layer that is nonmagnetic and includes a metal exhibiting a large spin Hall effect to react to a charge current directed into the spin Hall effect metal layer to produce a spin-polarized current that is perpendicular to the charge current, the spin Hall effect metal layer being parallel to and adjacent to the free magnetic layer to direct the spin-polarized current generated in the spin Hall effect metal layer into the free magnetic layer;
a first electrical terminal in electrical contact with the MTJ from a side having the pinned magnetic layer to receive a gate voltage that modifies a current threshold of a spin-polarized current flowing across the MTJ for switching the magnetization of the free magnetic layer; and
second and third electrical terminals in electrical contact with two contact locations of the spin Hall effect metal layer on two opposite sides of the free magnetic layer to supply the charge current in the spin Hall effect metal layer; and

wherein the row and column conductive lines include (1) row spin Hall effect metal stripes, each row spin Hall effect metal stripe being configured to be in contact with a row of memory cells as the spin Hall effect metal layer for each memory cell in the row of memory cells and further coupled to the memory control circuit to carry a row charge current as the charge current for each memory cell in the row of memory cells, and (2) column conductive stripes, each column conductive stripe being configured to be in contact with a column of memory cells respectively located in different rows of memory cells and further coupled to the memory control circuit to apply a row gate voltage as the gate voltage, or a row read voltage as the read voltage, for each memory cell in the column of memory cells; and
wherein the memory control circuit is coupled to the array of the memory cells and the row and column conductive lines to select one or more memory cells to supply to each selected memory cell (1) the charge current via the second and third electrical terminals in the spin Hall effect metal layer and (2) the gate voltage across the MTJ causing a small current tunneling across the MTJ that is insufficient to switch the magnetization of the free magnetic layer without collaboration of the spin-polarized current flowing across the free magnetic layer caused by the charge current.

2. The device as in claim 1 , wherein:
the memory control circuit includes:
a plurality of first transistors coupled to the column conductive stripes, respectively, one first transistor per column conductive stripe to apply the row gate voltage or the row read voltage to the first electrical terminals of the memory cells; and
a plurality of second transistors coupled to the row spin Hall effect metal stripes, respectively, one second transistor per row spin Hall effect metal stripe to connect to the second electrical terminals to switch on or off the row charge current in the respective row spin Hall effect metal stripe as the charge current for each memory cell in a corresponding row of memory cells.

3. The device as in claim 2 , wherein:
the memory control circuit includes a plurality of third transistors coupled to the row spin Hall effect metal stripes, respectively, one third transistor per row spin Hall effect metal stripe to connect between the third electrical terminals of memory cells in a corresponding row of memory cells and an electrical ground.

4. The device as in claim 3 , wherein:
the memory control circuit is configured to, in reading a selected memory cell, (1) turn on all of the first transistors to apply the row read voltage to the first electrical terminals of all of the memory cells, (2) turn off all of the second transistors and (3) turn on one third transistor in a corresponding row spin Hall effect metal stripe in contact with the selected memory cell while turning off other third transistors.

5. The device as in claim 3 , wherein:
the memory control circuit is configured to, in writing to a selected memory cell, (1) turn on one first transistor coupled to a column conductive stripe in contact with the selected memory cell while turning off other first transistors to apply the row gate voltage to the first electrical terminal of the selected memory cell, and (2) turn on one second transistor and one third transistor in one row spin Hall effect metal stripe in contact with the selected memory cell while turning off other second and third transistors.

6. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes tantalum or a tantalum alloy.

7. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes hafnium or a hafnium alloy.

8. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes iridium or an iridium alloy.

9. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes rhenium or a rhenium alloy.

10. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes osmium or an osmium alloy.

11. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes thallium or a thallium alloy.

12. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes lead or a lead alloy.

13. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes tungsten metal or a tungsten alloy.

14. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes a transition metal or a transition metal alloy.

15. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes Cu1-x Bi x, Ag1-xBix, Cu1-xIrx, Ag1-xIrx, Cu1-xWx, Ag1-xWx, Cu1-xTax, or Ag1-xTax.

16. The device as in claim 14 , wherein:
the spin Hall effect metal layer includes Pd, Mo, Ru, Ir, Au, Pt, or Bi.

17. The device as in claim 1 , wherein:
the spin Hall effect metal layer includes an intermetallic compound with an A15 crystal structure.

18. The device as in claim 1 , wherein:
the spin Hall effect metal layer has a thickness that is less than or equal to five times of a spin diffusion length of the spin Hall effect metal layer.

19. The device as in claim 1 , wherein:
the spin Hall effect metal layer has a thickness greater than a spin relaxation length of the spin Hall effect metal layer.

20. The device as in claim 1 , wherein:
the pinned or free magnetic layer includes Fe, Co, Ni, or an alloy including Fe, Co or Ni.

21. The device as in claim 1 , wherein:
the insulator material for the non-magnetic junction layer between the magnetic

Assignees

• Univ Cornell

Inventors

• Buhrman Robert A
• Ralph Daniel C
• Pai Chi-Feng
• Liu Luqiao

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/10

  Electricity · mapped topic

• H01L43/065

  Electricity · mapped topic

• H01L43/06

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic