Adjustable read reference voltage to reduce errors in memory devices

Patent metadata

Field	Value
Publication number	US-9947380-B2
Application number	US-201615267093-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Mar 11, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

According to one embodiment, a memory includes a magnetoresistive element, a reference cell, a sense amplifier comparing a first current flowing in the magnetoresistive element with a second current flowing in the reference cell, a first transistor having a first control terminal controlling a value of the first current, a second transistor having a second control terminal controlling a value of the second current, and a controller applying a first potential to the first control terminal and a second potential to the second control terminal in a first operation, and applying the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation.

First claim

What is claimed is:

1. A memory comprising:
a magnetoresistive element;
a reference cell;
a sense amplifier which compares a first current flowing in the magnetoresistive element with a second current flowing in the reference cell;
a first transistor having a first control terminal which controls a value of the first current;
a second transistor having a second control terminal which controls a value of the second current; and
a controller which applies a first potential to the first control terminal and a second potential to the second control terminal in a first operation for reading data from the magnetoresistive element, and which applies the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation for reading data from the magnetoresistive element.

2. The memory of claim 1 , further comprising:
a potential selector which selects one of the second and third potentials based on a select signal from the controller.

3. A memory comprising:
a magnetoresistive element;
a reference cell;
a sense amplifier which compares first current flowing in the magnetoresistive element with a second current flowing in the reference cell;
a first transistor having a first control terminal which controls a value of the first current;
a second transistor having a second control terminal which controls a value of the second current; and
a controller which applies a first potential to the first control terminal and a second potential to the second control terminal in a first operation, and which applies the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation,
wherein the magnetoresistive element has one of a first resistance and a second resistance, and the reference cell has a resistance between the first and second resistances.

4. The memory of claim 3 , wherein the reference cell has the resistance of a center of the first and second resistances.

5. The memory of claim 1 , wherein a value of the second current is between a value of the first current when the magnetoresistive element has the first resistance and a value of the first current when the magnetoresistive element has the second resistance in the first operation.

6. The memory of claim 1 , wherein the magnetoresistive element has a third resistance smaller than each of the first and second resistances in a defective state, and the second operation is an operation detecting the defective state.

7. The memory of claim 6 , wherein a value of the second current is between a value of the first current when the magnetoresistive element has the first resistance or the second resistance and a value of the first current when the magnetoresistive element has the third resistance in the second operation.

8. The memory of claim 6 , wherein the magnetoresistive element comprises a first magnetic layer, a second magnetic layer and an insulating layer between the first and second magnetic layers, and the defective state is a state in which the insulating layer has a dielectric breakdown.

9. The memory of claim 8 , wherein the first and second magnetic layers have magnetization directions respectively in a direction in which the first and second magnetic layers are stacked.

10. The memory of claim 6 , wherein the controller manages the magnetoresistive element with the defective state.

11. A memory comprising:
a variable resistance element;
a reference cell;
a sense amplifier which compares a first current flowing in the variable resistance element with a second current flowing in the reference cell;
a first transistor having a first control terminal which controls a value of the first current;
a second transistor having a second control terminal which controls a value of the second current; and
a controller which applies a first potential to the first control terminal and a second potential to the second control terminal in a first operation for reading from the variable resistance element, and which applies the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation for reading from the variable resistance element.

12. The memory of claim 3 , wherein a value of the second current is between a value of the first current when the magnetoresistive element has the first resistance and a value of the first current when the magnetoresistive element has the second resistance in the first operation.

13. The memory of claim 3 , wherein the magnetoresistive element has a third resistance smaller than each of the first and second resistances in a defective state, and the second operation is an operation detecting the defective state.

14. The memory of claim 13 , wherein a value of the second current is between a value of the first current when the magnetoresistive element has the first resistance or the second resistance and a value of the first current when the magnetoresistive element has the third resistance in the second operation.

15. The memory of claim 13 , wherein the magnetoresistive element comprises a first magnetic layer, a second magnetic layer and an insulating layer between the first and second magnetic layers, and the defective state is a state in which the insulating layer has a dielectric breakdown.

16. The memory of claim 15 , wherein the first and second magnetic layers have magnetization directions respectively in a direction in which the first and second magnetic layers are stacked.

Assignees

• Toshiba Memory Corp

Inventors

• Nakayama Masahiko
• Kawamura Masashi
• Hoya Katsuhiko
• Miyata Mikio
• Amano Minoru

Classifications

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title