Semiconductor memory device, a memory module including the same, and a memory system including the same

Patent metadata

Field	Value
Publication number	US-9947378-B2
Application number	US-201715729771-A
Country	US
Kind code	B2
Filing date	Oct 11, 2017
Priority date	May 29, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).

First claim

What is claimed is:

1. A method of operating a memory controller, comprising:
receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH);
determining a reference voltage according to the VOH; and
comparing the data signal with the reference voltage to determine a received data value,
wherein the VOH is proportional to a power supply voltage (VDDQ).

2. The method of claim 1 , wherein the VOH has a value of VDDQ/2.5.

3. The method of claim 1 , wherein the VOH has a value of VDDQ/3.

4. The method of claim 1 , wherein a value of the VOH depends on a resistance of an on-die termination (ODT) resistor of the memory controller.

5. The method of claim 4 , wherein the VOH has a value of VDDQ/2.5 when the ODT resistor is 80, 120 or 240 ohms.

6. The method of claim 4 , wherein the VOH has a value of VDDQ/3 when the ODT resistor is 40, 60, 80, 120 or 240 ohms.

7. The method of claim 1 , wherein the data signal is generated at the memory device in response to an instruction from the memory controller.

8. The method of claim 7 , wherein the instruction includes information about the VOH.

9. The method of claim 7 , wherein the instruction includes information about an on-die termination (ODT) resistor of the memory controller.

10. The method of claim 7 , wherein the instruction causes a mode register set (MRS) signal to be generated by the memory device.

11. The method of claim 10 , wherein the MRS signal varies according to the value of an on-die termination (ODT) resistor of the memory controller.

12. The method of claim 1 , wherein a mode register in the memory device includes information about an on-die termination (ODT) resistor of the memory controller.

13. The method of claim 1 , wherein the memory device performs a calibration based on a mode register set (MRS) signal generated according to a target VOH and an on-die termination (ODT) value of the memory controller.

14. A memory controller, comprising:
an on-die termination (ODT) resistor and a DQ pad, wherein the memory controller is configured to:
receive, via the DQ pad, a data signal from a memory device, wherein the data signal has an output high level voltage (VOH);
determine a reference voltage according to the VOH; and
compare the data signal with the reference voltage to determine a received data value,
wherein the VOH is proportional to a power supply voltage (VDDQ).

15. The controller of claim 14 , wherein ODT resistor has a value of 40, 60, 80, 120 or 240 ohms.

16. A method of operating a memory controller, comprising:
receiving a first data signal having a first output high level voltage (VOH), wherein the first VOH is proportional to a power supply voltage (VDDQ);
outputting a command instructing a VOH of a second data signal to be changed; and
receiving the second data signal, wherein the second data signal has the changed VOH, the changed VOH being proportional to VDDQ,
wherein the first VOH and the changed VOH are different from each other.

17. The method of claim 16 , wherein the first VOH is VDDQ/3.

18. The method of claim 16 , wherein the changed VOH varies with an impedance of an on-die termination (ODT) resistor of the memory controller.

19. The method of claim 16 , wherein the changed VOH is obtained by increasing or decreasing the VOH of the first data signal.

20. The method of claim 16 , wherein the command includes information about an impedance of an on-die termination (ODT) resistor of the memory controller.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Lee Ki Won
• Bae Seung Jun
• Park Joon Young
• Bae Yong Cheol

Classifications

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• H03K19/0005

  Modifications of input or output impedance · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title