Memory-aware matrix factorization

Patent metadata

Field	Value
Publication number	US-9947073-B2
Application number	US-201715431986-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Jun 18, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.

First claim

What is claimed is:

1. A computer program product for performing memory-aware matrix factorization on a graphics processing unit, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining one or more types of memory on the graphics processing unit;
determining one or more characteristics of each of the one or more types of memory;
assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics; and
executing the matrix factorization algorithm on the graphics processing unit,
wherein the one or more types of memory includes a cache memory having a texture memory that is used to cache read-only entries from a global memory, and
wherein the one or more types of memory further includes a register memory.

2. The computer program product of claim 1 , wherein the assignment of the plurality of memory accesses is configured to store hotspot variables in the cache memory.

3. The computer program product of claim 1 , wherein the characteristics include at least one of a memory size, an access latency, and a read/write permission.

4. The computer program product of claim 1 , wherein the texture memory is further used to store cached entries from the global memory.

5. A graphics processing unit for performing memory-aware matrix factorization, comprising:
a processor in communication with one or more types of memory, the processor configured to:
determine the one or more types of memory on the graphics processing unit;
determine one or more characteristics of each of the one or more types of memory;
assign each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics; and
execute the matrix factorization algorithm on the graphics processing unit,
wherein the one or more types of memory includes a cache memory having a texture memory that is used to cache read-only entries from a global memory, and
wherein the one or more types of memory further includes a register memory.

6. The graphics processing unit of claim 5 , wherein the assignment of the plurality of memory accesses is configured to store hotspot variables in the cache memory.

7. The graphics processing unit of claim 5 , wherein the characteristics include at least one of a memory size, an access latency, and a read/write permission.

8. The graphics processing unit of claim 5 , wherein the texture memory is further used to store cached entries from the global memory.

Assignees

• IBM

Inventors

• Cao Liangliang
• Fong Liana L
• Tan Wei

Classifications

• G06T1/60 Primary

  Memory management · CPC title

• H03M13/6566

  Implementations concerning memory access contentions · CPC title

• G06F3/0601

  Interfaces specially adapted for storage systems · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title