Automatic prioritization of interrupts in a modeling environment

Patent metadata

Field	Value
Publication number	US-9946668-B1
Application number	US-201414286359-A
Country	US
Kind code	B1
Filing date	May 23, 2014
Priority date	Jan 10, 2007
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

In one embodiment, a method of implementing interrupt prioritization and preemption in a modeling environment is provided. The method may include obtaining a model including interrupt-generating components in the modeling environment, obtaining information describing interrupts in the model, and using the information describing the interrupts in the model to automatically generate code for prioritizing the interrupts in the modeling environment.

First claim

We claim:

1. A method comprising:
receiving information associated with asynchronous interrupts in a block diagram model that models behavior of a dynamic system when executed,
the block diagram model including blocks that represent each represent a hardware device or subsystem,
the blocks being interconnected by lines that represent signals,
the signals corresponding to time-varying quantities and representing inputs and outputs of the dynamic system,

the asynchronous interrupts being generated by the blocks in the block diagram model,
the information associated with the asynchronous interrupts including:
information associated with a first interrupt and a second interrupt, and
information associated with priorities of the asynchronous interrupts,

a target system being configured to process the asynchronous interrupts,
the target system being configured to service the first interrupt and the second interrupt via a non-prioritized interrupt handling method, and
the receiving the information associated with the asynchronous interrupts being performed by a device;

assigning, based on the information associated with the priorities of the asynchronous interrupts, a first priority to the first interrupt,
the assigning the first priority being performed by the device;

assigning, based on the information associated with the priorities of the asynchronous interrupts, a second priority to the second interrupt,
the second priority being higher than the first priority, and
the assigning the second priority being performed by the device;

generating, based on the first priority and the second priority, code that, when executed on the target system, causes the target system to place servicing the first interrupt on hold upon receiving the second interrupt,
the generating the code being performed by the device; and

causing the target system to execute the code,
the causing the target system to execute the code being performed by the device,
the code including an interrupt service routine (ISR) for the first interrupt,
the code, when executed on the target system, causing the target system to execute the ISR based on receiving the first interrupt, and
the ISR causing the target system to:
store information associated with an original hardware configuration for the blocks,
set a new hardware configuration, for the blocks, that allows implementing an interrupt prioritization based on the first priority,
call a task that corresponds to the first interrupt, and
restore the original hardware configuration, for the blocks, based on the information associated with the original hardware configuration.

2. The method of claim 1 , where the ISR causes the target system to:
receive the first interrupt;
start servicing of the first interrupt;
receive the second interrupt;
place the servicing of the first interrupt on hold; and
start servicing of the second interrupt.

3. The method of claim 2 , where the ISR causes the target system to resume the servicing of the first interrupt after completing the servicing of the second interrupt.

4. The method of claim 2 , further comprising:
assigning a third priority to a third interrupt,
the third priority being lower than the first priority,
the ISR causing the target system to:
receive the third interrupt after starting the servicing of the first interrupt, and
place servicing of the third interrupt on hold.

5. The method of claim 4 , where the ISR causes the target system to start the servicing of the third interrupt upon completing the servicing of the first interrupt.

6. The method of claim 4 , where the ISR causes the target system to start the servicing of the third interrupt a preset time after starting the servicing of the first interrupt.

7. The method of claim 1 , further comprising:
receiving information using an interface; and
assigning the first priority or the second priority based on the information received using the interface.

8. The method of claim 1 , where:
the first priority is determined based on a priority of a first task associated with the first interrupt, and
the second priority is determined based on a priority of a second task associated with the second interrupt.

9. A system comprising:
one or more processors to:
receive information associated with asynchronous interrupts in a block diagram model that models behavior of a dynamic system when executed,
the block diagram model including blocks that each represent a hardware device or subsystem,
the blocks being interconnected by lines that represent signals,
the signals corresponding to time-varying quantities and representing inputs and outputs of the dynamic system,

the asynchronous interrupts being generated by the blocks in the block diagram model,
the information associated with the asynchronous interrupts including:
information associated with a first interrupt and a second interrupt, and
information associated with priorities of the asynchronous interrupts,

a target system being configured to process the asynchronous interrupts, and
the target system being configured to service the first interrupt and the second interrupt via a non-prioritized interrupt handling method;

assign, based on the information associated with the priorities of the asynchronous interrupts, a first priority to the first interrupt;
assign, based on the information associated with the priorities of the asynchronous interrupts, a second priority to the second interrupt,
the second priority being higher than the first priority;

generate, based on the first priority and the second priority, code that, when executed on the target system, causes the target system to place servicing the first interrupt on hold upon receiving the second interrupt; and
cause the target system to execute the code,
the code including an interrupt service routine (ISR) for the first interrupt,

the code, when executed on the target system, causing the target system to execute the ISR based on receiving the first interrupt, and
the ISR causing the target system to:
store information associated with an original hardware configuration for the blocks,
set a new hardware configuration, for the blocks, that allows implementing an interrupt prioritization based on the first priority,
call a task that corresponds to the first interrupt, and
restore the original hardware configuration, for the blocks, based on the information associated with the original hardware configuration.

10. The system of claim 9 , where the one or more processors are further to:
upon starting servicing of the first interrupt, disable servicing of interrupts with priorities lower than or equal to the first priority; and
enable servicing of interrupts with priorities higher than the first priority.

11. The method of claim 1 , where storing the information associated with the original hardware configuration includes storing information associated with one or more hardware registers.

12. The method of claim 1 , where the ISR causes the target system to:
enable the second interrupt; and
disable a third interrupt to which a third priority is assigned,
the third priority being lower than the first priority.

13. The method of claim 12 , where the ISR causes the target system to:
disable a fourth interrupt to which a fourth priority is assigned,
the fourth priority being equal to the first priority.

14. The method of claim 1 , where:
the ISR is a first ISR;
the code includes a second ISR for the second interrupt; and
the code, when executed on the target system, causes the target system to execute the

Assignees

• Mathworks Inc

Inventors

• Galijasevic Zijad
• Ancelle Antonin
• Belge Murat

Classifications

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F13/26 Primary

  with priority control · CPC title