Double-mix Feistel network for key generation or encryption

Patent metadata

Field	Value
Publication number	US-9946662-B2
Application number	US-201414472978-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A method of providing security in a computer system includes dividing a block of data into initial left and right halves, and calculating updated left and right halves for each of a plurality of rounds. Calculating the updated left half includes applying a first function to an input left half to produce a first result, and mixing the first result with an input right half. Calculating the updated right half includes applying a second function to the input left half to produce a second result, and mixing the second result with a round key. The input left and right halves are the initial left and right halves for the first round, and thereafter the updated left and right halves for an immediately preceding round. And method may include producing a block of ciphertext with a key composed of the updated left and right halves for the last round.

First claim

What is claimed is:

1. A system for providing security in a computer system, the system comprising one or more logic circuits configured to at least:
produce a block of data from a respective address of a memory location in a memory; divide the block of data into an initial left half and initial right half;
calculate an updated left half and an updated right half for each round of a plurality of rounds,
wherein the one or more logic circuits being configured to calculate the updated left half includes being configured to apply a first function to an input left half to produce a first result, and mix the first result with an input right half,
wherein the one or more logic circuits being configured to calculate the updated right half includes being configured to apply a second function to the input left half to produce a second result, and mix the second result with a round key, the input left half to which the first function is applied being identical to the input left half to which the second function is applied, and
wherein the input left half and input right half are the initial left half and initial right half for a first of the plurality of rounds, and the updated left half and updated right half for an immediately preceding round for each round thereafter;

produce a block of ciphertext with a key composed of the updated left half and updated right half for a last of the plurality of rounds; and
perform a write operation to write the block of ciphertext at the memory location having the respective address.

2. The system of claim 1 , wherein the first function is a non-linear function, and the second function is an invertible function.

3. The system of claim 1 ,
wherein the memory includes a window of memory locations each of which stores a respective block of ciphertext produced with a respective key that changes from memory location to memory location.

4. The system of claim 3 , wherein the one or more logic circuits being configured to produce the block of data includes being configured to produce the block of data further from a version value that is updated with each write operation at the memory location having the respective address, and
wherein each memory location of the window of memory locations stores the respective block of ciphertext produced with the respective key that also depends on the version value and thereby changes with each write operation.

5. The system of claim 1 , wherein the one or more logic circuits being configured to divide the block of data includes being configured to divide the block of data into the initial left half (L 0 ) and initial right half (R 0 ),
wherein the one or more logic circuits being configured to calculate the updated left half and updated right half includes being configured to calculate for each round i=0, 1, . . . , n:
L i+1 =F ( L i )⊕ R i , and

R i+1 =G ( L i )⊕ k i ,

wherein L i+1 and R i+1 represent the updated left half and updated right half, F and G represent the first function and second function, ⊕ represents an arithmetic addition or bitwise exclusive-or (XOR) operation, and k i represents the round key, and
wherein the one or more logic circuits being configured to produce the block of ciphertext includes being configured to produce the block of ciphertext with the key (L n+1 , R n+1 ).

6. A system for providing security in a computer system, the system comprising one or more logic circuits configured to at least:
receive a block of plaintext;
produce a block of ciphertext from the block of plaintext, wherein the one or more logic circuits being configured to produce the block of ciphertext includes being configured to at least:
divide the block of plaintext into an initial left half and initial right half; and
calculate an updated left half and an updated right half for each round of a plurality of rounds,
wherein the one or more logic circuits being configured to calculate the updated left half includes being configured to apply a first function to an input left half to produce a first result, and mix the first result with an input right half,
wherein the one or more logic circuits being configured to calculate the updated right half includes being configured to apply a second function to the input left half to produce a second result, and mix the second result with a round key, the input left half to which the first function is applied being identical to the input left half to which the second function is applied, and
wherein the input left half and input right half are the initial left half and initial right half for a first of the plurality of rounds, and the updated left half and updated right half for an immediately preceding round for each round thereafter, and

wherein the one or more logic circuits being configured to produce the block of ciphertext includes being configured to produce the block of ciphertext composed of the updated left half and updated right half for a last of the plurality of rounds; and
perform a write operation to write the block of ciphertext at a memory location having a respective address.

7. The system of claim 6 , wherein the first function is a non-linear function, and the second function is an invertible function.

8. The system of claim 6 , wherein the one or more logic circuits are further configured to at least:
produce the round key for each round of the plurality of rounds based on the respective address of a memory location in a memory,
wherein the one or more logic circuits being configured to perform the write operation includes being configured to perform the write operation to write the block of ciphertext at the memory location having the respective address, and
wherein the memory includes a window of memory locations each of which stores a respective block of ciphertext produced with a respective key that changes from memory location to memory location.

9. The system of claim 8 , wherein the one or more logic circuits being configured to produce the key includes being configured to produce the key further from a version value that is updated with each write operation at the memory location having the respective address, and
wherein each memory location of the window of memory locations stores the respective block of ciphertext produced with the respective key that also depends on the version value and thereby changes with each write operation.

10. The system of claim 6 , wherein the one or more logic circuits being configured to divide the block of plaintext includes being configured to divide the block of plaintext into the initial left half (L 0 ) and initial right half (R 0 ),
wherein the one or more logic circuits being configured to calculate the updated left half and updated right half includes being configured to calculate for each round i=0, 1, . . . , n:
L i+1 =F ( L i )⊕ R i , and

R i+1 =G ( L i )⊕ k i ,

wherein L i+1 and R i+1 represent the updated left half and updated right half, F and G represent the first function and second function, ⊕ represents an arithmetic addition or bitwise exclusive-or (XOR) operation, and k i represents the round key, and
wherein the one or more logic circuits being configured to produce the block of ciphertext includes being configured to produce the block of ciphertext (L n+1 , R n+1 ).

11. A method of providing security in a computer system, the method comprising:
producing a block of data from a respective address of a memory location in a memory; dividing the block of data into an initial left half and initial right half;
calculating an updated left half and an updated right half for each round of a plurality of rounds,
wherein calcu

Assignees

• Boeing Co

Inventors

• Hars Laszlo

Classifications

• G06F21/85

  interconnection devices, e.g. bus-connected or in-line devices · CPC title

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title