Holographic display

US9946224B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9946224-B2
Application numberUS-201615148142-A
CountryUS
Kind codeB2
Filing dateMay 6, 2016
Priority dateMay 16, 2007
Publication dateApr 17, 2018
Grant dateApr 17, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is a holographic display including a spatial light modulator (SLM) with pixels, the SLM pixels being on a substrate, the SLM including circuitry which is on the same substrate as the SLM pixels, the circuitry operable to perform calculations which provide an encoding of the SLM.

First claim

Opening claim text (preview).

We claim: 1. A holographic display comprising a spatial light modulator (SLM) with pixels on a substrate, the SLM: comprising circuitry on the substrate, the circuitry comprising circuitry elements in the form of transistors performing hologram calculations and distributed between the pixels of the SLM, the transistors integrated between, or next to, circuitry elements performing pixel control; the SLM substrate geometrically divided into clusters tiled over the SLM substrate, a cluster comprising a multitude of pixels and said circuitry elements in the form of transistors performing hologram calculations and being able to generate hologram data for holographic encoding of the SLM using real space image data, where data exchange is provided between neighboring clusters. 2. The holographic display of claim 1 , wherein the clusters are small identical parts. 3. The holographic display of claim 1 , further comprising a coherent or partially coherent light source emitting coherent or partially coherent light onto the pixels of the SLM. 4. The holographic display of claim 1 , wherein the pixel comprise transmissive cells. 5. The holographic display of claim 1 , wherein real space image data consists of intensity and depth map data. 6. The holographic display of claim 1 , wherein real space image data is a difference between successive real space image frames, where the real space image data is used in a holographic calculation, where holographic display data comprises sub-hologram difference data and display memory location data, and where said holographic display data is sent to the holographic display clusters. 7. The holographic display of claim 1 , wherein hologram encoding data is calculated outside a space occupied by the pixels, the hologram encoding data is then compressed using known data compression techniques, and is then transmitted to the circuitry on the SLM substrate, the circuitry then performing a function of decompressing the data which has been received. 8. The holographic display of claim 1 , wherein eye tracking is implemented. 9. The holographic display of claim 1 , wherein a lens optical aberration effect is reduced by correcting dynamically through the encoding of the spatial light modulator or in which speckle correction is implemented. 10. The holographic display of claim 1 , wherein the circuitry includes thin film transistors. 11. The holographic display of claim 1 , wherein the substrate is monocrystalline Si or in which the display is fabricated using liquid crystal on silicon technology. 12. The holographic display of claim 1 , wherein the substrate is glass. 13. The holographic display of claim 1 , wherein holographic calculations are performed in real time or in quasi real time or in which holographic calculations are performed using a look-up table approach. 14. The holographic display of claim 1 , wherein computation or generation is performed using sub-holograms. 15. The holographic display of claim 14 , wherein data for adding the sub-holograms is exchanged over a distance of a sub-hologram dimension or over a distance of a cluster dimension. 16. The holographic display of claim 1 , wherein holographic calculations are spread homogeneously over the circuitry on the SLM substrate. 17. The holographic display of claim 1 , wherein the holographic display is a high resolution display or in which the holographic display comprises a resolution being higher than the resolution of a high resolution display. 18. The holographic display of claim 1 , wherein a virtual observer window comprises a size being adaptable to the size of an eye pupil diameter or more across and in which for each virtual observer window, one depth map and intensity map pair is constructed. 19. The holographic display of claim 1 , wherein a display panel is controlled using conventional display technologies. 20. The holographic display of claim 1 , wherein an additional logic for local forwarding of calculated data exists, and the additional logic is co-used for forwarding an original image to clusters, so that at least some global row and column wires are eliminated. 21. The holographic display of claim 1 , wherein redundant circuitry, such as TFTs, is manufactured in a space of the pixels so that some redundant circuitry is used to replace circuitry used at device start up, where circuitry used at device start up is found to have failed.

Assignees

Inventors

Classifications

  • G03H1/0443Primary

    Digital holography, i.e. recording holograms with digital recording means (holobject computation G03H1/0866) · CPC title

  • Digital representation · CPC title

  • Low coherence light normally not allowing valuable record or reconstruction (G03H1/06 takes precedence) · CPC title

  • for video-holography, i.e. integrating hologram acquisition, transmission and display · CPC title

  • Details {of features involved during the holographic process; Replication of holograms without interference recording} · CPC title

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Frequently asked questions

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What does patent US9946224B2 cover?
Disclosed is a holographic display including a spatial light modulator (SLM) with pixels, the SLM pixels being on a substrate, the SLM including circuitry which is on the same substrate as the SLM pixels, the circuitry operable to perform calculations which provide an encoding of the SLM.
Who is the assignee on this patent?
Seereal Tech S A
What technology area does this patent fall under?
Primary CPC classification G03H1/0443. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 17 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).