Single-exposure high dynamic range CMOS image sensor pixel with internal charge amplifier
US-9106851-B2 · Aug 11, 2015 · US
US9942502B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9942502-B2 |
| Application number | US-201514633552-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 27, 2015 |
| Priority date | Mar 25, 2014 |
| Publication date | Apr 10, 2018 |
| Grant date | Apr 10, 2018 |
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A pixel architecture having an in-pixel amplifier comprising an NMOS transistor and a depletion-mode NMOS load is disclosed. In one aspect, the pixel architecture comprises a pixel core including a pixel photodiode for generating an output signal in accordance with incident light. Further, the in-pixel amplifier is connected to a pixel core to amplify the output signal before it is stored in a column buffer before being read out at output of the pixel architecture. By having an in-pixel amplifier that can be used for amplification of the output signal inside the pixel architecture, a larger output value is obtained which may be stored inside the pixel architecture on a small capacitor with improved signal-to-noise performance. This in-pixel amplification can also improve the quality of stored signals for global shutter operation.
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What is claimed is: 1. A pixel architecture comprising: a photodiode element operable for generating a signal; an in-pixel amplifier configured to amplify the generated signal and having a gain greater than one, the in-pixel amplifier comprising an NMOS amplifier with a depletion-mode NMOS load transistor, wherein the depletion-mode NMOS load transistor functions as a load of the NMOS amplifier; an output for outputting the amplified signal. 2. The pixel architecture according to claim 1 , further comprising at least one storage element connected to the in-pixel amplifier for storing the amplified signal. 3. The pixel architecture according to claim 1 , further comprising a plurality of storage elements connected to the in-pixel amplifier for storing the amplified signal, wherein one of the storage elements is provided for storing the amplified signal for each frame of a plurality of imaging frames, the storage elements being connected in parallel to the in-pixel amplifier and to the output. 4. The pixel architecture according to claim 1 , further comprising a column buffer connected to the output, the column buffer including at least one transistor for reading out signals for the output. 5. The pixel architecture according to claim 1 , wherein the photodiode element forms part of a pixel core, the pixel core including a floating diffusion region, a conversion capacitor, and at least one control transistor, the output from the pixel core forming an input for the in-pixel amplifier. 6. The pixel architecture according to claim 5 , wherein the in-pixel amplifier comprises an active amplifier forming part of a double sampling arrangement. 7. The pixel architecture according to claim 6 , wherein the double sampling arrangement comprises an input sampling capacitor connected to the pixel core and to the active amplifier, and a feedback capacitor connected between an input and an output of the active amplifier. 8. The pixel architecture according to claim 5 , wherein the at least one control transistor comprises a reset gate for resetting the photodiode element. 9. The pixel architecture according to claim 5 , wherein the at least one control transistor comprises a transfer gate for transferring the charge from the photodiode element to the floating diffusion region and a reset gate for resetting the photodiode element. 10. An imaging sensor comprising a plurality of pixels having a pixel architecture according to claim 1 . 11. The imaging sensor according to claim 10 , comprising a global shutter imaging sensor.
Control of the dynamic range · CPC title
comprising storage means other than floating diffusion · CPC title
applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title
Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title
Electricity · mapped topic
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