Apparatus for improved encoding and associated methods

Patent metadata

Field	Value
Publication number	US-9942063-B2
Application number	US-201314142639-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Oct 26, 2012
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An apparatus includes an encoder adapted to encode data bits for transmission via a communication link using pulse amplitude modulation (PAM). The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length and/or improve the DC balance of the data bits.

First claim

The invention claimed is:

1. An apparatus, comprising:
an encoder circuit that encodes data bits for transmission as a data stream via a communication link using pulse amplitude modulation (PAM), the encoder circuit comprising:
a bit order scrambling circuit that, based on a run-length of the data bits, generates encoded data bits having a DC imbalance smaller than a DC imbalance of the data bits by assigning a corresponding new bit location to each bit of the data bits and moving each bit of the data bits to the corresponding new bit location; and
a logic circuit configured to perform a logic operation on a pattern of bits and the data bits based on the DC imbalance of the data bits to generate the encoded data bits having the DC imbalance that is smaller than the DC imbalance of the data bits, wherein the logic operation is performed based on the run-length of the data and based on a subset of transition types.

2. The apparatus according to claim 1 , wherein the bit order scrambling circuit selectively assigns the corresponding new bit location to each bit of the data bits.

3. The apparatus according to claim 2 , wherein the bit order scrambling circuit assigns the corresponding new bit location to each bit of the data bits based on one or more of: (a) a cost function and (b) a DC balance estimation of the apparatus.

4. The apparatus according to claim 1 , wherein the bit order scrambling circuit assigns the corresponding new bit location to each bit of the data bits based on the run-length of the data based on a subset of transition types.

5. The apparatus according to claim 1 , wherein the logic operation comprises an addition modulus depending on an order of the PAM used in the communication link.

6. The apparatus according to claim 1 , wherein the logic operation is performed based on one or more of: (a) a cost function and (b) a DC balance estimation of the apparatus.

7. The apparatus according to claim 1 , wherein respective outputs of the bit order scrambling circuit and the logic circuits are selectively used to generate the encoded data bits.

Assignees

• Altera Corp

Inventors

• Mendel David W

Classifications

• H03M5/145 Primary

  Conversion to or from block codes or representations thereof · CPC title

• H04L25/08 Primary

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title