Free space optical data transmission for secure computing

Patent metadata

Field	Value
Publication number	US-9941962-B2
Application number	US-201615168267-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Apr 14, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An apparatus and method for computer network security based on Free-Space Optical Interconnections (FSOI) for board-to-board information transmission. The addition of a controllable, interlocked shutter system creates air-gapped isolation of the boards, allowing for increased obfuscation, and enhanced security.

First claim

What is claimed is:

1. A secure computer network architecture, comprising:
a plurality of processor components; and
at least one network communications component; wherein
at least one processor component comprises:
means for bidirectional optical data transfer with
said at least network communications component; and
at least one of said plurality of processor components; and

means for unidirectional optical data transfer with a remainder of said plurality of processor components; and
a means for interrupting said bidirectional optical data transfer;

said secure computer network architecture further comprising a non-transitory storage medium having a plurality of executable computer programming instructions stored therein, which, when executed by said at least one processor component, cause said at least one processor component to:
permit said network communications component to access data from external networks when
said means for bidirectional optical data transfer between said network communications component and a first processor component is verified as enabled;

transfer said data to said first processor component; and
transfer said data from said first processor component to a second processor component when
said data requires storage; and
said means for bidirectional optical data transfer between said network communications processor and said first processor component is verified as disabled.

2. The secure computer network architecture of claim 1 , wherein said executable computer programming instructions further cause said at least one processor component to:
transfer data from said second processor component to said first processor component when
said data requires transmission from said second processor component to said network communications component storage; and
said means for bidirectional optical data transfer between said network communications processor and said first processor component is verified as disabled;

transfer data from said first processor component to said network communications component when
said means for bidirectional optical data transfer between said second processor component and said first processor component is verified as disabled.

3. The secure computer network architecture of claim 2 , wherein said executable computer programming instructions further cause said at least one processor component to:
transfer data from a third processor component to said first processor component when
data is created on said third processor component that must be communicated; and
said means for bidirectional optical data transfer between said network communications component and said third processor component is verified as disabled; and

transfer data from said network communications component to external networks when
said means for bidirectional optical data transfer between said network communications component and said first processor component is verified as enabled.

4. The secure computer network architecture of claim 2 , wherein said executable computer programming instructions further cause said at least one processor component to:
store registry and operating system data in a secure repository created on a fourth processor component;
set a periodic time to scrub said first processor component; and
set a time delay to commence said scrub;
transfer said data from said secure repository in fourth processor component to said first processor component and scrub said first processor component when there is no user on said first processor component;
commence a countdown of said time delay;
notify a user that said scrub will commence at the expiration of said countdown;
transfer data from said secure repository in said fourth processor component to said first processor component; and

scrub said first processor component.

Assignees

• Us Air Force

Inventors

• Telesca Donald A

Classifications

• G06F21/606 Primary

  by securing the transmission between two devices or processes · CPC title

• G05D1/08

  Control of attitude, i.e. control of roll, pitch, or yaw · CPC title

• H04B10/118

  specially adapted for satellite communication · CPC title

• H04B10/801

  using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title

• H04L29/06

  Electricity · mapped topic