Self resetting latch

Patent metadata

Field	Value
Publication number	US-9941872-B2
Application number	US-201615358617-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Mar 31, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.

First claim

What is claimed is:

1. An apparatus comprising:
a first clocked latch stage producing first and second outputs using a first positive feedback circuit, and including first and second input transistors each having a first conductivity type, the first and second input transistors having respective control terminals respectively coupled to first and second inputs; and
a second clocked latch stage producing third and fourth outputs using a second positive feedback circuit, and including:
a third transistor coupled to the first output and having a second conductivity type that is different from the first conductivity type, and
a fourth input transistor coupled to the second output and having the second conductivity type,

wherein the first input is different from the third output and different from the fourth output, and
wherein the second input is different from the third output and different from the fourth output.

2. The apparatus of claim 1 ,
wherein the first clocked latch stage provides a first reset value to each of the first and second outputs when the first positive feedback circuit is turned off, and
wherein the second clocked latch stage provides a second reset value different from the first reset value to the third and fourth outputs when the second positive feedback circuit is turned off.

3. The apparatus of claim 2 ,
wherein the first and second input transistors provide the first reset value to the first and second outputs, respectively, when the first positive feedback circuit is turned off; and
wherein the third and fourth input transistors provide the second reset value to the third and fourth outputs, respectively, when the second positive feedback circuit is turned off.

4. The apparatus of claim 2 ,
wherein when the first positive feedback circuit is turned on, the first clocked latch stage provides a first current according to a first input signal to the first output using the first input transistor and provides a second current according to a second input signal to the second output using the second input transistor, the first and second signals being respectively received on the first and second inputs; and
wherein when the second positive feedback circuit is turned on, the second clocked latch stage provides a third current according to a value of the first output to the third output using the third input transistor and a fourth current according to a value of the second output to the fourth output using the fourth input transistor.

5. The apparatus of claim 2 ,
wherein the second positive feedback circuit is turned on when the first positive feedback circuit is turned on; and
wherein the second positive feedback circuit is turned off when the first positive feedback circuit is turned off.

6. The apparatus of claim 1 ,
wherein the first positive feedback circuit feeds back a value of a difference between the first and second outputs to the first and second outputs when the first positive feedback circuit is turned on; and
wherein the second positive feedback circuit feeds back a value of a difference between the third and fourth outputs to the third and fourth outputs when the second positive feedback circuit is turned on.

7. The apparatus of claim 1 ,
wherein the first clocked latch stage comprises:
the first input transistor having a control terminal configured to receive a first input signal and a conduction terminal coupled to the first output,
the second input transistor having a control terminal configured to receive a second input signal and a conduction terminal coupled to the second output, and
the first feedback circuit coupled to the first and second outputs; and

wherein the second clocked latch stage comprises:
the third input transistor having a control terminal coupled to the first output and a conduction terminal couple to the third output,
the fourth input transistor having a control terminal coupled to the second output and a conduction terminal couple to the fourth output, and
the second feedback circuit coupled to the third and fourth outputs.

8. An apparatus comprising:
a first clocked latch stage producing first and second outputs using a first positive feedback circuit, and including first and second input transistors each having a first conductivity type; and
a second clocked latch stage producing third and fourth outputs using a second positive feedback circuit, and including:
a third transistor coupled to the first output and having a second conductivity type that is different from the first conductivity type, and
a fourth input transistor coupled to the second output and having the second conductivity type; and

a supply voltage circuit configured to provide, to the first and second input transistors, a power supply voltage having a voltage value according to a voltage value of the second input signal and a value of a reference current,
wherein when the first positive feedback circuit is turned on, the first clocked latch stage provides a first current according to a first input signal to the first output using the first input transistor and provides a second current according to a second input signal to the second output using the second input transistor, and
wherein when the second positive feedback circuit is turned on, the second clocked latch stage provides a third current according to a value of the first output to the third output using the third input transistor and a fourth current according to a value of the second output to the fourth output using the fourth input transistor.

9. The apparatus of claim 8 , further comprising:
a first replica transistor substantially identical to the second input transistor,
wherein the voltage value of the power supply voltage is equal to a sum of the voltage value of the second input signal and a voltage drop across the first replica transistor, and
wherein the voltage drop across the first replica transistor is produced according to the value of the reference current.

10. A method comprising:
generating, by a first clocked latch stage using a first positive feedback circuit, first and second outputs, the first clocked latch stage including first and second input transistors each having a first conductivity type, the first and second input transistors having respective control terminals respectively coupled to first and second inputs; and
generating, by a second clocked latch stage using a second positive feedback circuit, third and fourth outputs, the second clocked latch stage including:
a third transistor coupled to the first output and having a second conductivity type that is different from the first conductivity type, and
a fourth input transistor coupled to the second output and having the second conductivity type,

wherein the first input is different from the third output and different from the fourth output, and
wherein the second input is different from the third output and different from the fourth output.

11. The method of claim 10 , further comprising:
providing, by the first clocked latch stage, a first reset value to each of the first and second outputs when the first positive feedback circuit is turned off,
providing, by the second clocked latch stage, a second reset value different from the first reset value to each of the third and fourth outputs when the first positive feedback circuit is turned off.

12. The method of claim 11 , further comprising:
providing the first reset value to the first and second outputs using the first and second input transistors, respectively, when the first positive feedback circuit is turned off; and
providing the second reset value to the third and fourth outputs using the t

Assignees

• Marvell Int Ltd

Inventors

• Cyrusian Sasan

Classifications

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03K5/249 Primary

  using clock signals · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03K3/356113

  using additional transistors in the input circuit · CPC title