Apparatus for design for testability of multiport register arrays

Patent metadata

Field	Value
Publication number	US-9941866-B2
Application number	US-201615207800-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Jul 12, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

First claim

What is claimed is:

1. A register array comprising:
a first flip-flop latch array including:
a first set of master latches;
a first set of slave latches coupled to the first set of master latches; and
a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;

a second flip-flop latch array including:
a second set of master latches;
a second set of slave latches coupled to the second set of master latches; and
a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port; and
an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configurable to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

2. The register array of claim 1 , further comprising a write decoder and a read decoder, the write decoder configured to write enable the first flip-flop latch array and the second flip-flop latch array in a functional mode, the read decoder configured to read enable the first flip-flop latch array and the second flip-flop latch array in the functional mode.

3. The register array of claim 2 , further comprising a plurality of 1-bit flip-flops, the plurality of 1-bit flip-flops each comprising a master latch and a slave latch, the plurality of flip-flops addressable from at least one of the read decoder and the write decoder.

4. The register array of claim 1 , wherein the first address port includes a first write address port and a first read address port, and the second address port includes a second write address port and a second read address port.

5. The register array of claim 1 , wherein the first flip-flop latch array is a first size having a depth N and the second flip-flop latch array is a second size having a depth M, and wherein the first size and the second size are not equal.

6. The register array of claim 5 , wherein the first address port is configured to receive n address bits and the second address port is configured to receive m address bits, wherein m≠n and wherein n=log 2 (N) and m=log 2 (M).

7. The register array of claim 6 , wherein the address counter comprises an n-bit counter and wherein n>m.

8. The register array of claim 7 , wherein n bits of the counter are coupled to the first flip-flop latch array and m least significant bits of the counter are coupled to the second flip-flop latch array.

9. The register array of claim 1 , wherein the first set of slave latches are addressed for a read using at least one multiplexer and wherein an output of at least one of the at least one multiplexer is coupled to a first input to an AND gate, a second input to the AND gate coupled to a shift data signal, and an output of the AND gate coupled to a shift out data signal.

10. A method comprising:
operating a first flip-flop latch array, the first flip-flop latch array including:
a first set of master latches;
a first set of slave latches coupled to the first set of master latches; and
a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;

operating a second flip-flop latch array, the second flip-flop latch array including:
a second set of master latches;
a second set of slave latches coupled to the second set of master latches; and
a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port; and
operating an address counter, the address counter coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

11. The method of claim 10 , further comprising operating a write decoder and a read decoder, the write decoder configured to write enable the first flip-flop latch array and the second flip-flop latch array in a functional mode, the read decoder configured to read enable the first flip-flop latch array and the second flip-flop latch array in the functional mode.

12. The method of claim 11 , further comprising operating a plurality of 1-bit flip-flops concurrently during the test mode, the plurality of 1-bit flip-flops each comprising a master latch and a slave latch, the plurality of flip-flops addressable from at least one of the read decoder and the write decoder.

13. The method of claim 10 , wherein the first address port includes a first write address port and a first read address port, and the second address port includes a second write address port and a second read address port.

14. The method of claim 10 , wherein the first flip-flop latch array is a first size and the second flip-flop latch array is a second size, and wherein the first size and the second size are not equal.

15. The method of claim 14 , wherein the first address port is configured to receive n address bits and the second address port is configured to receive m address bits, and wherein m≠n.

16. The method of claim 15 , wherein the address counter comprises an n-bit counter and wherein n>m.

17. The method of claim 16 , wherein n bits of the counter are coupled to the first flip-flop latch array and m least significant bits of the counter are coupled to the second flip-flop latch array.

18. The method of claim 10 , wherein the first set of slave latches are addressed for a read using at least one multiplexer and wherein an output of at least one of the at least one multiplexer is coupled to a first input to an AND gate, a second input to the AND gate coupled to a shift data signal, and an output of the AND gate coupled to a shift out data signal.

19. A register array comprising:
means for operating a first flip-flop latch array, the first flip-flop latch array including:
a first set of master latches;
a first set of slave latches coupled to the first set of master latches; and
a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;

means for operating a second flip-flop latch array, the second flip-flop latch array including:
a second set of master latches;
a second set of slave latches coupled to the second set of master latches; and
a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port; and
means for operating an address counter, the address counter coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

20. The register array of claim 19 , further comprising means for op

Assignees

• Qualcomm Inc

Inventors

• Vattikonda Rakesh
• Sinharoy Samrat
• Lu de

Classifications

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title