MOS transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9941416-B2
Application number	US-201615356022-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Aug 24, 2015
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a silicon on insulator substrate having a semiconductor substrate coated with an insulating layer and with a semiconductor layer;
a MOS transistor gate supported by a portion of the semiconductor layer forming a channel region and a portion of the insulating layer which insulates the channel region from the semiconductor substrate;
an epitaxial source region and epitaxial drain region on opposite sides of the channel region, wherein the epitaxial source region and epitaxial drain region have a depth from a bottom of the MOS transistor gate that is deeper than a depth of the channel region from the bottom of the MOS transistor gate; and
an insulating region insulating a bottom of the epitaxial source region and epitaxial drain region from the semiconductor substrate;
wherein the insulating region comprises:
an insulating oxide material liner that lines the bottom of the epitaxial source region and epitaxial drain region, a side of the portion of the insulating layer under the channel region and an upper surface of the semiconductor substrate; and
an insulating nitride material fill in contact with the insulating liner.

2. The integrated circuit of claim 1 , wherein the channel region and the epitaxial source region and epitaxial drain region have a coplanar upper surface.

3. The integrated circuit of claim 1 , wherein the insulating oxide material liner is also present on side walls of the MOS transistor gate.

4. The integrated circuit of claim 1 , wherein the insulating oxide material liner and insulating nitride material fill are also present on side walls of the MOS transistor gate.

5. The integrated circuit of claim 1 , wherein the insulating oxide material liner and insulating nitride material fill are also present on side walls of the epitaxial source region and epitaxial drain region.

6. The integrated circuit of claim 1 , wherein the insulating nitride material fill is positioned between a bottom surface of each of the epitaxial source region and epitaxial drain region and a top surface of the semiconductor substrate.

7. The integrated circuit of claim 6 , wherein a first portion of the insulating oxide material liner is positioned between the bottom surface of each of the epitaxial source region and epitaxial drain region and a top surface of the insulating nitride material fill.

8. The integrated circuit of claim 7 , wherein a first portion of the insulating oxide material liner is positioned between a bottom surface of the insulating nitride material fill and the top surface of the semiconductor substrate.

9. An integrated circuit, comprising:
a silicon on insulator substrate having a semiconductor substrate coated with an insulating layer and with a semiconductor layer;
a MOS transistor gate supported by a portion of the semiconductor layer forming a channel region and a portion of the insulating layer which insulates the channel region from the semiconductor substrate;
an epitaxial source region and epitaxial drain region on opposite sides of the channel region, wherein the epitaxial source region and epitaxial drain region have a depth from a bottom of the MOS transistor gate that is deeper than a depth of the channel region from the bottom of the MOS transistor gate;
a first cavity between the epitaxial source region and the semiconductor substrate;
a second cavity between the epitaxial drain region and the semiconductor substrate;
an insulating oxide material liner that lines surfaces of the first and second cavities; and
an insulating nitride material fill within the first and second cavities to insulate the epitaxial source region and epitaxial drain region from the semiconductor substrate.

10. The integrated circuit of claim 9 , wherein the insulating nitride material fill is also present adjacent side walls of the MOS transistor gate.

11. The integrated circuit of claim 9 , wherein the channel region and the epitaxial source region and epitaxial drain region have a coplanar upper surface.

12. The integrated circuit of claim 9 , wherein the insulating oxide material liner lines a bottom surface of the epitaxial source and drain regions, a side wall of the portion of the insulating layer which insulates the channel region from the semiconductor substrate and an upper surface of the semiconductor substrate.

13. The integrated circuit of claim 12 , wherein the insulating oxide material liner further extends on side walls of the MOS transistor gate.

14. The integrated circuit of claim 12 , wherein the insulating oxide material liner further extends on side walls of the epitaxial source region and epitaxial drain region.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Bidal Gregory

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01304

  characterised by the conductor · CPC title

• H01L29/665

  Electricity · mapped topic