Semiconductor devices and methods for forming a semiconductor device

Patent metadata

Field	Value
Publication number	US-9941402-B2
Application number	US-201715627481-A
Country	US
Kind code	B2
Filing date	Jun 20, 2017
Priority date	Jun 28, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a guard structure located laterally between a first active area of a semiconductor substrate of the semiconductor device and a second active area of the semiconductor substrate, the guard structure comprising a first doping region located at a front side surface of the semiconductor substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region, the common doping region extending from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure; and
an edge termination doping region laterally surrounding the first active area and the second active area,
wherein the edge termination doping region and the first doping region of the guard structure comprise a first conductivity type and the common doping region comprises a second conductivity type,
wherein a resistive connection between the edge termination doping region and the first doping region of the guard structure is present at least during reverse operating conditions of the semiconductor device.

2. The semiconductor device of claim 1 , wherein the first doping region of the guard structure is in contact with the edge termination doping region so that the first doping region of the guard structure and the edge termination doping region are short circuited.

3. The semiconductor device of claim 1 , wherein a lateral part of the edge termination doping region and the first doping region of the guard structure laterally surround the first active area.

4. The semiconductor device of claim 1 , wherein the resistive connection is present during any operating condition of the semiconductor device.

5. The semiconductor device of claim 1 , wherein the highly doped portion of the common doping region laterally surrounds at least one of the first active area and the second active area.

6. The semiconductor device of claim 1 , further comprising a wiring layer stack disposed on the semiconductor substrate, wherein a vertical gap extends from a surface of the wiring layer stack at least to a portion of a pre-metal insulation layer located above the edge termination doping region or to a surface of the semiconductor substrate.

7. The semiconductor device of claim 1 , further comprising a wiring layer stack disposed on the semiconductor substrate, wherein the wiring layer stack is devoid of metal wiring structures above the edge termination doping region.

8. The semiconductor device of claim 1 , wherein a width of the first doping region of the guard structure is larger than 5 μm and less than 50 μm.

9. The semiconductor device of claim 1 , wherein a width of the edge termination doping region is larger than 500 nm and less than 10 μm.

10. The semiconductor device of claim 1 , wherein a maximal vertical dimension of the first doping region of the guard structure is larger than 200 nm and smaller than 10 μm.

11. The semiconductor device of claim 1 , wherein a maximal vertical dimension of the edge termination doping region is at most equal to a maximal vertical dimension of the first doping region of the guard structure.

12. The semiconductor device of claim 1 , wherein a maximal doping concentration of the first doping region of the guard structure is substantially equal to a maximal doping concentration of the edge termination doping region.

13. The semiconductor device of claim 1 , wherein at least one electrical element structure is located at the first active area, wherein the at least one electrical element structure comprises a first doping region of the first conductivity type adjacent to the common doping region, wherein during reverse operating conditions of the semiconductor device a p-n junction between the first doping region of the at least one electrical element structure and the common doping region is forward biased.

14. The semiconductor device of claim 13 , wherein the first doping region of the at least one electrical element structure is a body region of at least one transistor cell of the at least one electrical element structure.

15. The semiconductor device of claim 13 , wherein the at least one electrical element structure has a breakdown voltage higher than 10 V.

16. The semiconductor device of claim 13 , wherein the second active area comprises a well doping region of the first conductivity type, wherein doping regions of electrical elements of a control circuit are located at the well doping region of the second active area.

17. The semiconductor device of claim 16 , wherein the control circuit is configured to provide a gate voltage for the at least one electrical element structure of the first active area.

18. The semiconductor device of claim 17 , wherein the semiconductor device is configured to adjust the electric potential of the well doping region of the second active area based on the electric potential of the common doping region at the backside of the semiconductor substrate.

19. The semiconductor device of claim 1 , wherein the first doping region of the guard structure is laterally separated from the edge termination doping region, and wherein a minimal lateral distance between the first doping region of the guard structure and the edge termination doping region is less than 50 nm.

20. A method for forming a semiconductor device, the method comprising:
forming an edge termination doping region laterally surrounding a first active area of a semiconductor substrate of the semiconductor device and a second active area of the semiconductor substrate;
forming a first doping region of a guard structure located at a front side surface of the semiconductor substrate; and
forming a wiring structure of the guard structure electrically connecting the first doping region of the guard structure to a highly doped portion of a common doping region, the common doping region extending from a backside surface of the semiconductor substrate to at least a part of the front side surface of the semiconductor substrate in contact with the wiring structure of the guard structure, the guard structure being located laterally between the first active area and the second active area, the edge termination doping region and the first doping region of the guard structure comprising a first conductivity type and the common doping region comprising a second conductivity type,
wherein a resistive connection between the edge termination doping region and the first doping region of the guard structure is present at least during reverse operating conditions of the semiconductor device.

Assignees

• Infineon Technologies Ag

Inventors

• Finney Adrian
• Kotz Dietmar
• Cazimirovici Radu Eugen
• Ostermann Thomas

Classifications

• H10P34/40

  with high-energy radiation · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H01L21/823487

  Electricity · mapped topic

• H01L29/7811 Primary

  Electricity · mapped topic