Enhancement mode III-N HEMTs

Patent metadata

Field	Value
Publication number	US-9941399-B2
Application number	US-201615242266-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Apr 23, 2008
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

First claim

What is claimed is:

1. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a conductive gate contact, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof;
a source contact and a drain contact, wherein the source contact and the gate contact are each over the nitride channel layer and the drain contact is below on an opposite side of the nitride channel layer from the gate contact;
a GaN drift layer between the nitride channel layer and the drain contact; and
a current blocking layer between the nitride channel layer and the GaN drift layer,
wherein the first channel region is non-conductive in the absence of a switching voltage applied to the gate contact, but is conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate contact, and
wherein the device includes channel access regions on opposite sides of the first channel region, and the current blocking layer is below the channel access regions but not below the first channel region.

2. The device of claim 1 , wherein the GaN drift layer is a lightly doped (n−) layer.

3. The device of claim 1 , wherein the current blocking layer is a doped GaN layer.

4. A III-N semiconductor device comprising:
a nitride channel layer including a first channel region beneath a conductive gate contact, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof;
a source contact and a drain contact, wherein the source contact and the gate contact are each over the nitride channel layer and the drain contact is below on an opposite side of the nitride channel layer from the gate contact;
a GaN drift layer between the nitride channel layer and the drain contact; and
a current blocking layer between the nitride channel layer and the GaN drift layer;
a substrate; and
an additional nitride layer between the substrate and the GaN drift layer,
wherein a via is formed through the substrate and the drain makes contact with the additional nitride layer through the via, and
wherein the first channel region is non-conductive in the absence of a switching voltage applied to the gate contact, but is conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate contact.

5. The device of claim 4 , wherein the additional nitride layer comprises highly doped n+ GaN.

6. A III-N semiconductor device
a nitride channel layer including a first channel region beneath a conductive gate contact, the composition of the nitride channel layer being selected from the group consisting of nitrides of gallium, indium, aluminum, and combinations thereof;
a source contact and a drain contact, wherein the source contact and the gate contact are each over the nitride channel layer and the drain contact is below on an opposite side of the nitride channel layer from the gate contact; and
channel access regions on opposite sides of the first channel region,
wherein the device comprises an AlXN layer above the channel layer in the areas adjacent to the channel access regions but not in the area adjacent to the first channel region, wherein X is selected from the group consisting of gallium, indium or their combination, and
wherein the first channel region is non-conductive in the absence of a switching voltage applied to the gate contact, but is conductive in the presence of a switching voltage greater than a threshold voltage applied to the gate contact.

7. The device of claim 6 , wherein the device comprises an insulator layer between the gate contact and the nitride channel layer.

8. The device of claim 6 , wherein the device is an enhancement mode device.

Assignees

• Transphorm Inc

Inventors

• Mishra Umesh
• Coffie Robert
• Shen Likun
• Ben-Yaacov Ilan
• Parikh Primit

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/477 Primary

  Vertical HEMTs or vertical HHMTs · CPC title

• H01L21/0254

  Electricity · mapped topic