Semiconductor device having electrode and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9941372-B2
Application number	US-201615149773-A
Country	US
Kind code	B2
Filing date	May 9, 2016
Priority date	Feb 22, 2013
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device comprising:
forming a dummy gate over a semiconductor substrate;
forming a trench in an upper portion of the dummy gate;
forming a dielectric feature in the trench; and
after forming the dielectric feature, replacing the dummy gate with an electrode to form the semiconductor device comprising the dielectric feature and the electrode, the replacing comprising removing the dummy gate including removing a portion of the dummy gate under the trench.

2. The method of claim 1 , further comprising:
forming a high-k dielectric layer between the dielectric feature and the electrode.

3. The method of claim 1 , wherein a ratio of a thickness of the dielectric feature to a thickness of the electrode is from about 0.5 to about 0.75.

4. The method of claim 1 , wherein a ratio of a length of the dielectric feature to a length of the electrode is from about 0.1 to about 0.9.

5. The method of claim 1 , further comprising forming a spacer along sidewalls of the trench prior to forming the dielectric feature.

6. The method of claim 1 , wherein forming the dielectric feature comprises:
forming a dielectric layer over the dummy gate, the dielectric layer filling the trench and extending along sidewalls of the dummy gate; and
planarizing the dielectric layer, thereby forming the dielectric feature.

7. The method of claim 1 , wherein the removing comprises removing the dummy gate, thereby forming a recess extending under the dielectric feature, and the replacing the dummy gate with an electrode comprises:
forming a gate dielectric along a bottom and sidewalls of the recess and under the dielectric feature; and
filling the recess with a conductive material.

8. The method of claim 7 , further comprising forming an interfacial layer along a bottom of the recess prior to forming the gate dielectric.

9. A method of fabricating a semiconductor device comprising:
forming a sacrificial layer over a substrate, the sacrificial layer comprising a first material;
forming one or more first trenches in the sacrificial layer;
filling the one or more first trenches in the sacrificial layer with a second material, the first material being different than the second material, wherein a bottom of the second material filling the one or more trenches is above a bottom of the sacrificial layer;
removing the sacrificial layer to form a second trench; and
forming a conductive material in the second trench to form the semiconductor device comprising the second material and the conductive material, the conductive material extending between the second material and the substrate.

10. The method of claim 9 , wherein forming the sacrificial layer comprises forming a polysilicon layer.

11. The method of claim 10 , wherein the polysilicon layer is doped.

12. The method of claim 9 , further comprising forming an interlayer dielectric layer in the one or more first trenches and along sidewalls of a perimeter of the sacrificial layer.

13. The method of claim 12 , further comprising planarizing the interlayer dielectric layer to expose the sacrificial layer.

14. The method of claim 9 , wherein the one or more first trenches comprise a plurality of first trenches.

15. The method of claim 9 , further comprising forming spacers along sidewalls of the one or more first trenches prior to filling the one or more first trenches in the sacrificial layer with the second material.

16. A method of fabricating a semiconductor device comprising:
forming a dummy gate over a substrate, the dummy gate comprising a first material, the dummy gate having one or more first recesses;
completely filling the one or more first recesses with a second material, the first material and the second material being different material, wherein a bottom of the second material filling the one or more first recesses is above a bottom of the dummy gate;
removing the dummy gate to form a second recess; and
forming a conductive material in the second recess to form the semiconductor device comprising the second material and the conductive material.

17. The method of claim 16 , further comprising forming spacers in the one or more first recesses prior to filling the one or more first recesses with the second material.

18. The method of claim 16 , further comprising forming a high-k dielectric along a bottom and sidewalls of the second material prior to forming the conductive material.

19. The method of claim 18 , wherein a ratio of a thickness of the second material to a thickness of the high-k dielectric is from about 1 to about 10.

20. The method of claim 16 , wherein a ratio of a length of the second material to a length of the conductive material is from about 0.1 to about 0.9.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Pai-Chieh
• Wen Tsung Yao
• Chen Jyh-Huei

Classifications

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H01L29/4958

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic