Wrap-around contact on FinFET

Patent metadata

Field	Value
Publication number	US-9941367-B2
Application number	US-201615226557-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Apr 21, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

First claim

What is claimed is:

1. A structure comprising:
a fin structure on a substrate, the fin structure comprising an epitaxial region, the epitaxial region having an upper surface and an under-surface, wherein the upper surface faces away from the substrate and the under-surface faces toward the substrate;
an upper contact on the epitaxial region comprising a first metal layer over the upper surface, a first portion of a barrier layer over the first metal layer, and a first portion of a second metal layer on the first portion of the barrier layer; and
a lower contact on the epitaxial region comprising a metal-insulator-semiconductor (MIS) contact along the under-surface, the MIS contact comprising a dielectric layer on the under-surface, a second portion of the barrier layer on the dielectric layer, and a second portion of the second metal layer on the second portion of the barrier layer.

2. The structure of claim 1 , wherein the upper contact further comprises a metal-semiconductor compound between the epitaxial region and the first metal layer.

3. The structure of claim 1 further comprising an etch stop layer on a portion of the under-surface of the epitaxial region.

4. The structure of claim 1 , wherein the dielectric layer is titanium oxide (TiO 2 ), the first metal layer is titanium (Ti), and the barrier layer is titanium nitride (TiN).

5. The structure of claim 1 , wherein the epitaxial region is at least a portion of a source/drain region.

6. A semiconductor device comprising:
a fin formed over a substrate;
a gate structure formed over the fin, the gate structure comprising a gate dielectric and a gate electrode;
a source/drain structure formed over the fin and adjacent the gate structure;
a dielectric layer disposed on an underside of the source/drain structure;
a metal-semiconductor compound layer disposed on a top surface of the source/drain structure, wherein a portion of the underside of the source/drain structure is free of the metal-semiconductor compound layer;
a metal layer disposed on the metal-semiconductor compound layer; and
a conformal barrier layer disposed on the metal layer and the dielectric layer.

7. The semiconductor device of claim 6 , wherein the metal-semiconductor compound layer comprises a silicide.

8. The semiconductor device of claim 6 , wherein the metal-semiconductor compound layer comprises titanium (Ti), silicon (Si), and germanium (Ge).

9. The semiconductor device of claim 6 , wherein the metal-semiconductor compound layer is disposed on a portion of the underside of the source/drain structure.

10. The semiconductor device of claim 6 , further comprising a conductive material disposed on the conformal barrier layer.

11. The semiconductor device of claim 10 , wherein the conductive material, the conformal barrier layer, the dielectric layer, and the underside of the source/drain structure form a metal-insulator-semiconductor contact.

12. The semiconductor device of claim 6 , wherein the source/drain structure comprises a first epitaxial region disposed on a second epitaxial region.

13. The semiconductor device of claim 6 , further comprising an etch stop layer disposed on a portion of the underside of the source/drain structure.

14. The semiconductor device of claim 6 , wherein the source/drain structure is a first source/drain structure and further comprising a second source/drain structure formed over the fin opposite the gate structure from the first source/drain structure.

15. A semiconductor device comprising:
a first fin extending from a substrate;
a second fin extending from the substrate, the second fin adjacent to the first fin;
a first epitaxial region disposed on the first fin and a second epitaxial region disposed on the second fin, the first epitaxial region adjacent the second epitaxial region;
a metal layer disposed on a top surface of the first epitaxial region and on a top surface of the second epitaxial region;
a conformal dielectric layer disposed on and physically contacting an under surface of the first epitaxial region and disposed on and physically contacting an under surface of the second epitaxial region; and
a conformal barrier layer disposed on and extending continuously over the top surface of the first epitaxial region, the under surface of the first epitaxial region, the top surface of the second epitaxial region, and the under surface of the second epitaxial region.

16. The semiconductor device of claim 15 , wherein the conformal dielectric layer extends continuously from the under surface of the first epitaxial region to the under surface of the second epitaxial region.

17. The semiconductor device of claim 16 , further comprising a first etch stop layer contacting a portion of the under surface of the first epitaxial region and a portion of the under surface of the second epitaxial region, the first etch stop layer extending continuously from the under surface of the first epitaxial region to the under surface of the second epitaxial region.

18. The semiconductor device of claim 17 , further comprising a second etch stop layer disposed between the first etch stop layer and the conformal dielectric layer, the second etch stop layer having a different composition than the first etch stop layer.

19. The semiconductor device of claim 16 , further comprising a first metal-semiconductor compound layer disposed between the first epitaxial region and the metal layer.

20. The semiconductor device of claim 16 , further comprising a conductive material disposed over the conformal barrier layer and further comprising an enclosed void in the conductive material, wherein the enclosed void is between the first epitaxial region and the second epitaxial region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sung-Li
• Chen Neng-Kuo
• Shih Ding-Kang
• Chang Meng-Chun
• Lin Yi-An
• Huang Gin-Chen
• Hsu Chen-Feng
• Lin Hau-Yu
• Ko Chih-Hsin
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H01L27/0886

  Electricity · mapped topic

• H01L2029/7858

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic