Electro-static discharge protection circuit

Patent metadata

Field	Value
Publication number	US-9941267-B2
Application number	US-201414480995-A
Country	US
Kind code	B2
Filing date	Sep 9, 2014
Priority date	Sep 9, 2014
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

An electro-static discharge (ESD) protection circuit is configured to protect circuitry during an ESD event. The ESD protection circuit includes an ESD detection circuit and an ESD clamp circuit. The ESD clamp circuit includes a stack of transistors that is controlled by the ESD detection circuit. A first stack transistor of the stack of transistors includes a deep n-well. The stack of transistors is configured to be activated responsive to detecting the ESD event. The stack of transistors is configured to be deactivated responsive to detecting at least one of normal current conditions or normal voltage conditions. The ESD detection circuit includes a string of diodes. The string of diodes is configured to be activated responsive to detecting the ESD event. The stack of transistors is configured to be a voltage divider responsive to normal voltage conditions.

First claim

What is claimed is:

1. An electro-static discharge (ESD) protection circuit, comprising:
an ESD clamp circuit comprising a stack of transistors; and
an ESD detection circuit, comprising:
a string of diodes, wherein a first end of the string of diodes is coupled to a first source/drain region of a first stack transistor of the stack of transistors;
a first transistor comprising a first source/drain region coupled to a first node between a first diode of the string of diodes and a second diode of the string of diodes, wherein a second source/drain region of the first transistor is coupled to a gate of the first stack transistor; and
a second transistor comprising a first source/drain region coupled to the second source/drain region of the first transistor and the gate of the first stack transistor, wherein:
a second source/drain region of the second transistor is coupled to the first end of the string of diodes and the first source/drain region of the first stack transistor; and
a gate of the second transistor is coupled to a gate of the first transistor.

2. The ESD protection circuit of claim 1 , wherein the first source/drain region of the first stack transistor and the first end of the string of diodes are commonly coupled to a first voltage source.

3. The ESD protection circuit of claim 1 , wherein the stack of transistors comprises a second stack transistor coupled in series with the first stack transistor.

4. The ESD protection circuit of claim 3 , wherein a first source/drain region of the second stack transistor is coupled to a second source/drain region of the first stack transistor and a second source/drain region of the second stack transistor is coupled to a second end of the string of diodes.

5. The ESD protection circuit of claim 4 , wherein a body of the first stack transistor is coupled to the second source/drain region of the first stack transistor.

6. The ESD protection circuit of claim 3 , wherein the first stack transistor is an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and the second stack transistor is a second n-channel MOSFET.

7. An electro-static discharge (ESD) protection circuit, comprising:
an ESD detection circuit, comprising:
a string of diodes coupled between a first voltage source and a second voltage source; and
a first transistor, wherein:
a gate of the first transistor is coupled to the first voltage source,
a first source/drain region of the first transistor is coupled to a first node between a first diode of the string of diodes and a second diode of the string of diodes, and
a gate of the first transistor is coupled to a gate of a second transistor that is coupled between the first voltage source and a second source/drain region of the first transistor; and

an ESD clamp circuit coupled to the ESD detection circuit, wherein the ESD clamp circuit comprises a stack of transistors coupled between the first voltage source and the second voltage source.

8. The ESD protection circuit of claim 7 , wherein the string of diodes comprises a deep n-well.

9. The ESD protection circuit of claim 7 , wherein the first transistor comprises a deep n-well.

10. The ESD protection circuit of claim 7 , wherein:
the stack of transistors comprises a first stack transistor,
a first source/drain region of the first stack transistor is coupled to the first voltage source, and
a gate of the first stack transistor is coupled to the second source/drain region of the first transistor.

11. The ESD protection circuit of claim 10 , wherein:
the stack of transistors comprises a second stack transistor,
a first source/drain of the second stack transistor is coupled to a second source/drain region of the first stack transistor,
a gate of the second stack transistor is coupled to the ESD detection circuit, and
a body of the second stack transistor is coupled to a second source/drain region of the second stack transistor and to the second voltage source.

12. The ESD protection circuit of claim 10 , wherein the first stack transistor comprises a deep n-well.

13. The ESD protection circuit of claim 7 , wherein:
the ESD detection circuit comprises a third transistor,
a first source/drain region of the third transistor is coupled to the second source/drain region of the first transistor,
the ESD clamp circuit comprises a first stacked transistor, and
a second source/drain region of the third transistor is coupled to a gate of the first stacked transistor.

14. The ESD protection circuit of claim 13 , wherein the first source/drain region of the first transistor is coupled to a gate of the third transistor.

15. The ESD protection circuit of claim 13 , wherein:
the ESD detection circuit comprises a resistor,
the first diode, the second diode, and the first source/drain region of the first transistor are commonly coupled at the first node, and
a gate of the third transistor is coupled to the first node through the resistor.

16. The ESD protection circuit of claim 13 , wherein:
the ESD clamp circuit comprises a second stacked transistor,
the second source/drain region of the first transistor is coupled to a gate of the second stacked transistor, and
the first source/drain region of the third transistor is coupled to the gate of the second stacked transistor.

17. The ESD protection circuit of claim 16 , wherein the first stacked transistor is arranged in series with the second stacked transistor.

18. An electro-static discharge (ESD) protection circuit, comprising:
an ESD detection circuit, comprising:
a string of diodes coupled between a first voltage source and a second voltage source;
a first transistor;
a second transistor; and
a third transistor, wherein:
a gate of the first transistor is coupled to the first voltage source,
a first source/drain region of the first transistor and a gate of the second transistor are coupled to a first node between a first diode of the string of diodes and a second diode of the string of diodes, and
a first source/drain region of the second transistor is coupled to a gate of the third transistor; and

an ESD clamp circuit coupled to the ESD detection circuit, wherein the ESD clamp circuit comprises a first stack transistor and a second stack transistor.

19. The ESD protection circuit of claim 18 , wherein a second source/drain region of the first transistor is coupled to a gate of the first stack transistor.

20. The ESD protection circuit of claim 18 , the ESD detection circuit comprising a fourth transistor coupled between the first voltage source and a second source/drain region of the first transistor, wherein a gate of the fourth transistor is coupled to the gate of the first transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Ming Hsien

Classifications

• H01L27/0266 Primary

  Electricity · mapped topic

• H01L27/0285

  Electricity · mapped topic

• H10D89/819

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/811 Primary

  using FETs as protective elements · CPC title